Hardware overview

The Qualcomm Dragonwing^TM IQ-8275 Evaluation Kit (EVK) has Qualcomm IQ-8275 SoC mounted on the mainboard. Learn more about the system block diagram, electrical design, features, and capabilities of the EVK.

System block diagram

The following figure shows the system block diagram of the Dragonwing IQ-8275 EVK platform. This figure provides a visual representation of the platform’s architecture, highlighting the main components and their interactions. Figure : Dragonwing IQ-8275 EVK system block diagram

Hardware specification

The following table outlines the key hardware specification of the Dragonwing IQ-8275 EVK. Note For the list of interfaces supported in this release, see the Qualcomm Linux 2.0 Release Notes. Table : Dragonwing IQ-8275 EVK key specifications

Interface or feature	Description
SoC	IQ-8275
Memory	4 × 16 bit 12 GB LP5 3200 MHz (2 x 6 GB LPDDR5)
PMIC	2 × PMM8620AU
External MCU	Not present
Storage	1 × 128 GB UFS, micro-SD card or eMMC on main card, 1 x EEPROM for MACs.
Display	Four display ports: • 2 × mini-DP (through KTM switch) • DSI flex connection (display not included)
DSI flex connection with touchscreen
Camera/Video input	3 × Quad deserializers
3 × CSI (C-PHY or D-PHY) cameras
USB	USB0 Type-C (host or device mode)
USB1 uUSB 2.0 (host or device mode)
WLAN/Bluetooth®	M.2 module (NFA765A)
2 × printed antennas (Bluetooth shared with one WLAN antenna)
PCIe	Mainboard supported or expanded options (selected through switch): • 1 × PCIe x4 slot or expansion (switch) • 1 × M.2 E key (WI-Fi) or expansion (switch) • QPS615 PCIe expansion is supported through a mezzanine board.
Audio	1 × I2 S mic
2 × I2 S speaker amps
Additional I2 S on GPIOs
Ethernet	RJ45 2.5 GbE MD
Additional ethernet ports can be added using mezzanine interface cards.
CAN/CAN-FD	1 × CAN/CAN-FD on low speed header on mainboard
Low-speed expansion	3.3 V header for developer community with CAN, SPI, I2 C, UART, I2 S
Second low-speed expansion	QUPs and GPIOs on mezzanine connectors
Sensors	IMU: ICM-42688
QUPs on expansion
Trusted platform module (TPM)	ST33HTPH2x32AHE4 on mainboard

Exterior view

The following figures show the exterior of the Dragonwing IQ-8275 EVK with the bottom case. Figure : Exterior view of the EVK with bottom case The following figures show the side views of the Dragonwing IQ-8275 EVK, with labeled ports, connectors, and switches. The following figure shows the top view of the core board. Figure : Top view of the core board

EVK ports and interfaces

The following figure shows a detailed view of all the connectors on the Dragonwing IQ-8275 EVK. Figure : Connectors on Dragonwing IQ-8275 EVK The following figure shows the platform with few cables plugged in. Figure : Platform with cables plugged in Table : Connectors and functions

Connectors	Functions
JPWR	DC power (barrel connector) plug, 12 V–36 V input voltage
JLS1	Low speed IO header receptacle (LS1)
SW1	8 position surface mount DIP switch
SW2	4 position surface mount DIP switch
SW3	6 position surface mount DIP switch
JCAM0	MIPI CSI0 camera interconnect receptacle
JCAM1	MIPI CSI1 camera interconnect receptacle
JCAM2	MIPI CSI2 camera interconnect receptacle
JPCIE	PCI Express v4 receptacle connector (PCIe1)
JEDP1	EDP1 connector
JEDP0	EDP0 connector
JETH	Ethernet connector (2.5 GbE)
JUSB1	USB-C (USB Type-C) receptacle connector for USB1
JUSB0	USB-C (USB Type-C) receptacle connector for USB0
J13	Antenna for WLAN
S4	Slide switch for power or automation control
JDISP	Connector for DSI display
JTAC	Micro-USB receptacle for debug UART
JTAG	Header connector for JTAG
J14	Antenna for WLAN/Bluetooth
JEXP1–JEXP4	Board-to-board 120 position connector receptacle

DIP switch

The following images show the location of the DIP switches on the mainboard. Figure : DIP switches 1, 2, and 3 on Dragonwing IQ-8275 EVK Note If a DIP switch is facing up, it indicates that the switch is on. The following table details DIP switch operations for the Dragonwing IQ-8275 EVK, including functions and settings for board configuration. Table : DIP switch position and its respective functions

Switch	Connection when ON	Connection when OFF (default from factory)	Notes
SW1-1	PCIe0 is routed to mezzanine	PCIe0 is connected to the mainboard Wi-Fi module	None
SW1-2	PCIe1 is routed to mezzanine	PCIe1 is connected to the mainboard PCIe connector	None
SW1-3	NC	NC	None
SW1-4	DSI0 routed to mezzanine	DSI0 routed to mainboard DSI flex connector	None
SW1-5	CSI0 is routed to mezzanine	CSI0 is routed to the mainboard CSI flex connector	None
SW1-6	CSI1 is routed to mezzanine	CSI1 is routed to the mainboard CSI flex connector	None
SW1-7	CSI1 is routed to mezzanine	CSI2 is routed to the mainboard CSI flex connector	None
SW1-8	SDC signal will be routed to SD card	SDC signal will be routed to eMMC	None
SW2-1	Main domain forced USB boot/EDL	No impact	Currently, this switch isn’t enabled in software.
SW2-2	Main domain fast boot	No impact	None
SW2-3	Main domain and RTSS domain forced USB boot/EDL (combined)	No impact	Currently, the software implementation puts both domains into EDL mode together. It’s important for software download.
SW2-4	RTSS domain Fastboot mode	No impact	None
SW3-1	OSPI is routed to mezzanine	OSPI is connected to onboard memory for MCU	None
SW3-2	Force MD and MCU PS_HOLD	No impact	None
SW3-3	Watchdog is disabled	RAM dump is enabled	None
SW3-4	Boot from eMMC	Boot from UFS	eMMC located on interface and mezzanine
SW3-5	EUD enable	No impact	None
SW3-6	Skip MD BIST	No impact	None
SW4-1	PWM-MODE for fan set to low	PWM-MODE for fan set to high	Don’t change.
SW7-1	RGMII voltage select 2.5V	RGMII voltage select 1.8V	None
SW9-1	USB to m.2 connector for NFA765 module on mezzanine	USB to m.2 connector for NFA765 module on mainboard	None
SW8-1	RTSS CAN GPIOs routed to mezzanine	RTSS CAN GPIOs routed to JLS1 connector	None
S17	EMMC_THERM selected	UFS THERM selected	None
S18	UFS2.1 or eMMC version selected	UFS3.1 version is selected	None
S19	USB1_HS port selected	USB0_HS port is selected	None
S20	USB1_SS port selected	USB0_SS port is selected	None

LEDs

The Dragonwing IQ-8275 EVK has status LEDs that monitor system functions such as power-on and board faults, crucial for debugging and bringup. The following table lists and summarizes the functions of the LEDs. The Connectors on Dragonwing IQ-8275 EVK shows the location and the LEDs present on the board. Table : Summary of reference designator, location, color, and function of LEDs

Reference designator	Location	Color	Function
DS1	Mainboard	Green	Reserved for debugging
DS8	Mainboard	Green	Ethernet status LEDs
DS9	Mainboard	Green
DS10	Mainboard	Green	3.3 V LED
DS11	Mainboard	Orange	3.3 V LED

Hardware components and interfaces

The following are the high-level details of the Dragonwing IQ-8275 processor, power supply, memory, and various interfaces, such as camera, USB, and DisplayPort. It also includes sensors, flash memory, expansion options, a debug interface, audio support, thermal management, fan control, and accessory boards.

Processor

The target processor used in the Dragonwing IQ-8275 EVK is the Dragonwing IQ-8275 SoC, also known as the QCS8275. This SoC features an octa-core Kryo^™ Gen 6 CPU built on Arm v8.2 Cortex technology, with clock support up to 2.35 GHz. In addition to the eight high-performance CPU cores, the SoC includes a GPU and a Hexagon Tensor Processor with vector and matrix extensions, enabling the management of various concurrent compute and AI workloads simultaneously. The SoC offers extensive peripheral support, including integrated Ethernet, USB, Wi-Fi, PCIe, and Bluetooth. It’s capable of delivering up to 40 TOPS, making it suitable for powering high-performance, AI-centric, and Edge AI industrial use cases. The target applications include:

Factory automation
Industrial robots
Industrial personal computers
Drones
Edge AI Boxes
Machine Vision
Autonomous Mobile Robots (AMRs)
Industrial gateways

Power

The main power input to the Dragonwing IQ-8275 board is provided through the 2.10 mm barrel jack connector (JPWR, JACK-C-PC-10A-RA(R)), supporting an input voltage range of 12 V to 36 V. The EVK also includes a Type-C to barrel plug adapter. Four power management ICs manage the respective power supplies to various system blocks, including the SoC, PMIC, PCIe, and expansion ports.

Memory

The IQ-8275 EVK has two 6 GB LPDDR5 SDRAM ICs.

Camera interface

An analog switch is used for each MIPI CSI interface, allowing the MIPI CSI interfaces to be accessible through both the JCAM camera interconnect receptacle and the B2B expansion connector (JEXP4). To use a GMSL camera with the Dragonwing IQ-8275 EVK, connect it through the GMSL mezzanine, which must be ordered separately. The CSI ports are routed through the DIP switches, allowing configuration and setup. The three MIPI CSI ports operate in either C-PHY or D-PHY mode and support a range of existing cameras and flex cable. The following block diagrams show various CSI interfaces.

Figure : Camera CSI0 interfaces Figure : Camera CSI1 interfaces Figure : Camera CSI2 interfaces

USB interface

The board features three USB connectors: two Type-C connectors (JUSB0 and JUSB1) and one micro-USB connector (JUSB2). The following figures show the USB interfaces and configuration. USB0-SS interfaces and configuration USB0-HS interfaces and configuration USB2-HS interfaces and configuration USB interfaces and configuration

DisplayPort (eDP) interface

The target processor is equipped with 1 x eDP interface. EDP0 is routed to LT8713 EDP bridge as shown, with also a BYPASS option to JEDP0. The following figure shows the eDP interfaces and configuration. eDP interfaces and configuration

DSI interface

The IQ-8275 processor supports one 4-lane MIPI-DSI with VESA DSC v1.2. The Dragonwing IQ-8275 EVK uses an analog switch for DSI0 interface, allowing the interface to be accessible through both the JDISP LCD receptacle and the B2B expansion connector (JEXP1). The following figure shows the DSI connectors Figure : DSI connectors

Storage interfaces

The Dragonwing IQ-8275 has three types of storage interfaces: secure digital (SD) card, universal flash storage (UFS), and electrically erasable programmable read-only memory (EEPROM).

SD card

The target processor supports a single SDIO interface (SDC1). The SDC pins are routed through analog switches to facilitate connections through the micro SD card connector (JSDC) on the board, and eMMC (U150). The following figures show the SD card interfaces and configuration. SDIO card interfaces and configuration SD card interfaces and configuration

UFS

The target processor supports 1 x UFS 3.1 Gear 4 interface. UFS0 serves as the main domain boot-up device. The following table lists the part numbers and manufacturers of these UFS devices. Table : Part numbers and manufacturers of UFS devices

Reference designator	Interface identifier	MPN	Manufacturer	Description
U38	UFS0	THGJFGT0T25BAB8	KIOXIA AMERICA INC	128 GB UFS3.1 (Gear4) Q100-GR2 RoHS

The following figure shows the UFS interfaces and configuration. UFS interfaces and configuration

EEPROM

The Dragonwing IQ-8275 EVK platform has a single EEPROM device dedicated to storing MAC addresses for Ethernet, Wi-Fi, and Bluetooth. The following table lists the part number and manufacturer of the EEPROM device. Table : Part number and manufacturer of the EEPROM device

Reference designator	Device	MPN	Manufacturer	Description
U20	EEPROM	93LC46B-I/SN	Microchip Technology Inc.	1 Kbit low-voltage serial electrically erasable PROMs (EEPROM)

On-board sensors

The Dragonwing IQ-8275 EVK platform includes an on-board IMU and a temperature sensor. They are connected to the real-time subsystem (RTSS) domain of IQ-8275 EVK. Note Currently, the software doesn’t support the IMU and temperature sensors. Contact Qualcomm software team for details if you wish to enable them. The following table lists the part numbers and manufacturers of these sensors. Table : Part numbers and manufacturers of the sensors

Reference designator	Sensor type	Communication protocol used	MPN	Manufacturer
U97	IMU sensor	I²C	ICM-42688	TDK InvenSense
U109	Temperature sensor	SPI	TMP411DQDGKRQ1	Texas Instruments

PCIe interface

The target processor supports two PCIe interfaces: PCIe0 and PCIe1. PCIe0 is Gen4 2-lane and PCIe1 is Gen4 4-lane PCIe interface. Both PCIe interfaces are connected to an A/B switch, which by default, connects them to the expansion mezzanine. For DIP switch settings, see the Table: DIP switch position and its respective functions. The following figures show the PCIe interfaces and configuration. Figure : PCIe0 interfaces and configuration Figure : PCIe1 interfaces and configuration

Flash memory

The Dragonwing IQ-8275 EVK uses OSPI interface to support 2GBIT flash memory. The analog switch for OSPI interface allows the interface to be accessible through both the flash memory device and the B2B expansion connector (JEXP2). Note Due to the analog switch, you can connect the OSPI to the memory device or to B2B connector through DIP switch settings. For the intended OSPI settings, see the Table: DIP switch position and its respective functions. The following figure shows the flash memory interfaces and configuration. Figure : Flash memory interfaces and configuration The main board provides CAN0, and the JEXP1 connector provides CAN1-7. The following figures show controller area network (CAN) block diagram and interfaces. Figure : CAN0 interfaces

Expansion headers

The Dragonwing IQ-8275 EVK features four high-speed expansion connectors (JEXP1-4, 10139781-121422LF). Connect accessory cards such as GMSL mezzanine and RBx adapters to these connectors. Additionally, other interfaces mentioned throughout this document are also routed to these connectors, see the Connectors on Dragonwing IQ-8275 EVK. The following table details the pin mapping for the JEXP1 connector. Table : Pin mapping for the JEXP1 connector

Pin name	Pin number	Pin number	Pin name
GND	61	1	VREG_SYSTEM_PWR
DSI0_A0_LN0_P_CONN	62	2	VREG_SYSTEM_PWR
DSI0_B0_LN0_M_CONN	63	3	VREG_SYSTEM_PWR
GND	64	4	VREG_SYSTEM_PWR
DSI0_C0_LN1_P_CONN	65	5	VREG_SYSTEM_PWR
DSI0_A1_LN1_M_CONN	66	6	GND
GND	67	7	GND
DSI0_B1_CLK_P_CONN	68	8	GND
DSI0_C1_CLK_M_CONN	69	9	GND
GND	70	10	VREG_PMIC_IN_3P3
DSI0_A2_LN2_P_CONN	71	11	VREG_PMIC_IN_3P3
DSI0_B2_LN2_M_CONN	72	12	GND
GND	73	13	GND
DSI0_C2_LN3_P_CONN	74	14	PME_GPIO_3_USB1_FAULT_3P3_N
DSI0_NC_LN3_M_CONN	75	15	PME_GPIO_4_USB0_FAULT_3P3_N
GND	76	16	MD_GPIO_17_MDPX3_1P8
VREG_L6C_SENSOR_IO_1P8	77	17	MD_GPIO_18_MDPX3_1P8
GND	78	18	SGMII0_MDC_MDPX3_1P8
VREG_MDPX3_1P8	79	19	SGMII0_MDIO_MDPX3_1P8
GND	80	20	SGMII0_CONN_RX_P
IOEXPAN1_INT_MDPX3_1P8_N	81	21	SGMII0_CONN_RX_M
IOEXP5_IO_P2_1P8	82	22	SGMII0_CONN_TX_P
Not connected	83	23	SGMII0_CONN_TX_M
Not connected	84	24	SGMII0_INT_MDPX3_1P8_N
Not connected	85	25	SGMII0_RST_MDPX3_1P8_N
Not connected	86	26	JEXP1_MD_GPIO_45_MDPX3_1P8
IOEXP5_IO_P7_1P8	87	27	JEXP1_MD_GPIO_46_MDPX3_1P8
Not connected	88	28	JEXP1_MD_GPIO_47_MDPX3_1P8
RTSS_ERR0_SPX3_1P8	89	29	JEXP1_MD_GPIO_48_MDPX3_1P8
RTSS_CAN_SPI_MISO_SPX3_1P8	90	30	RTSS_CAN0_TX_SPX3_1P8
RTSS_SPI_MISO_SPX3_1P8	91	31	RTSS_CAN0_RX_SPX3_1P8
RTSS_CAN_SPI_MOSI_SPX3_1P8	92	32	RTSS_CAN1_TX_SPX3_1P8
RTSS_CAN_SPI_SCLK_SPX3_1P8	93	33	RTSS_CAN1_RX_SPX3_1P8
RTSS_CAN_SPI_CS_0_SPX3_1P8	94	34	RTSS_CAN2_TX_SPX3_1P8
RTSS_CAN_SPI_CS_1_SPX3_1P8	95	35	RTSS_CAN2_RX_SPX3_1P8
RTSS_IO_47_SPX3_1P8	96	36	RTSS_CAN3_TX_SPX3_1P8
RTSS_IO_48_SPX3_1P8	97	37	RTSS_CAN3_RX_SPX3_1P8
RTSS_IO_49_SPX3_1P8	98	38	Not connected
RTSS_IO_50_SPX3_1P8	99	39	Not connected
RTSS_PMIC_INT_SPX3_1P8_N	100	40	Not connected
RTSS_INT_SPX3_1P8_N	101	41	Not connected
RTSS_PWR_READY_SPX3_1P8	102	42	Not connected
RTSS_SLP_EN_SPX3_1P8	103	43	Not connected
RTSS_DBG_UART_TX_M_SPX3_1P8	104	44	Not connected
RTSS_DBG_UART_RX_M_SPX3_1P8	105	45	Not connected
GND	106	46	RTSS_CAN_INT0_SPX3_1P8
PCIE0_MEZZCONN_CLK_P	107	47	Not connected
PCIE0_MEZZCONN_CLK_N	108	48	RTSS_CAN_STB_0_SPX3_1P8
GND	109	49	Not connected
PCIE0_MEZZCONN_RX0_P	110	50	Not connected
PCIE0_MEZZCONN_RX0_N	111	51	Not connected
GND	112	52	RTSS_IO_2_SPX3_1P8
PCIE0_MEZZCONN_RX1_P	113	53	RTSS_IO_3_SPX3_1P8
PCIE0_MEZZCONN_RX1_N	114	54	Not connected
GND	115	55	PCIE0_MEZZCONN_RST_1P8_N
PCIE0_MEZZCONN_TX0_P	116	56	PCIE0_MEZZCONN_CLKREQ_1P8_N
PCIE0_MEZZCONN_TX0_N	117	57	PCIE0_MEZZCONN_WAKE_1P8_N
GND	118	58	MD_GPIO_78_GNSS_RESET_MDPX3_1P8
PCIE0_MEZZCONN_TX1_P	119	59	MD_GPIO_77_GNSS_EN_MDPX3_1P8
PCIE0_MEZZCONN_TX1_N	120	60	MD_GPIO_79_GNSS_BOOT_MODE_MDPX3_1P8

The following table details the pin mapping for the JEXP2 connector. Table : Pin mapping for the JEXP2 connector

Pin name	Pin number	Pin number	Pin name
VREG_MDPX3_1P8	61	1	VREG_SPX3_1P8
GND	62	2	GND
SOC_MI2S_MCLK0_MDPX3_1P8	63	3	VREG_SPX3_1P8
SOC_MI2S1_SCK_MDPX3_1P8	64	4	GND
SOC_MI2S1_WS_MDPX3_1P8	65	5	USB01_I2C_SDA_MDPX3_1P8
SOC_MI2S1_DATA0_MDPX3_1P8	66	6	USB01_I2C_SCL_MDPX3_1P8
SOC_MI2S1_DATA1_MDPX3_1P8	67	7	IOEXP5_IO_P1_1P8
MI2S2_SCK_MDPX3_1P8	68	8	VREG_1P2_EN
MI2S2_WS_MDPX3_1P8	69	9	USB_VBUS_DET_MDPX3_1P8
MI2S2_DATA0_MDPX3_1P8	70	10	USB_RESET_MDPX3_1P8_N
MI2S2_DATA1_MDPX3_1P8	71	11	USB1_ID_MDPX3_1P8
HS0_MI2S_SCK_CONN	72	12	USB0_ID_MDPX3_1P8
HS0_MI2S_WS_CONN	73	13	IOEXP5_IO_P0_1P8
HS0_MI2S_DATA0_CONN	74	14	IOEXP5_IO_P3_1P8
HS0_MI2S_DATA1_CONN	75	15	USB1_INT_MDPX3_1P8_N
HS1_MI2S_SCK_CONN	76	16	USB0_INT_MDPX3_1P8_N
HS1_MI2S_WS_CONN	77	17	MD_GPIO_65_MDPX3_1P8
HS1_MI2S_DATA0_CONN	78	18	EXP_I2C_SDA_MDPX3_1P8
HS1_MI2S_DATA1_CONN	79	19	EXP_I2C_SCL_MDPX3_1P8
HS2_MI2S_SCK_CONN	80	20	FAN_INT_MDPX3_1P8_N
HS2_MI2S_WS_CONN	81	21	HUB_P2_USB_HS_P
HS2_MI2S_DATA0_CONN	82	22	HUB_P2_USB_HS_M
HS2_MI2S_DATA1_CONN	83	23	HUB_P2_USB_SS_RX_P
SOC_QUA_MI2S_SCK_MDPX3_1P8	84	24	HUB_P2_USB_SS_RX_M
SOC_QUA_MI2S_WS_MDPX3_1P8	85	25	HUB_P2_USB_SS_TX_P
SOC_QUA_MI2S_DATA0_MDPX3_1P8	86	26	HUB_P2_USB_SS_TX_M
SOC_QUA_MI2S_DATA1_MDPX3_1P8	87	27	GND
SOC_QUA_MI2S_DATA2_MDPX3_1P8	88	28	HUB_P3_USB_HS_M
SOC_QUA_MI2S_DATA3_MDPX3_1P8	89	29	HUB_P3_USB_HS_P
SOC_I2S1_SCK_MDPX3_1P8	90	30	HUB_P3_USB_SS_TX_P
SOC_I2S1_WS_MDPX3_1P8	91	31	HUB_P3_USB_SS_TX_M
SOC_I2S1_DATA0_MDPX3_1P8	92	32	HUB_P3_USB_SS_RX_P
SOC_I2S1_DATA1_MDPX3_1P8	93	33	HUB_P3_USB_SS_RX_M
LPI_I2S2_CLK_MDPX3_1P8	94	34	GND
LPI_I2S2_WS_MDPX3_1P8	95	35	HUB_P4_USB_HS_M_2
LPI_I2S2_DATA0_MDPX3_1P8	96	36	HUB_P4_USB_HS_P_2
LPI_I2S2_DATA1_MDPX3_1P8	97	37	HUB_P4_USB_SS_TX_P
SOC_I2S3_SCK_MDPX3_1P8	98	38	HUB_P4_USB_SS_TX_M
SOC_I2S3_WS_MDPX3_1P8	99	39	HUB_P4_USB_SS_RX_P
SOC_I2S3_DATA0_MDPX3_1P8	100	40	HUB_P4_USB_SS_RX_M
SOC_I2S3_DATA1_MDPX3_1P8	101	41	GND
I2S4_SCK_MDPX3_1P8	102	42	RTSS_RGMII_RESET_SPX3_N
I2S4_WS_MDPX3_1P8	103	43	RTSS_RGMII_INT_SPX3_N
I2S4_DATA0_MDPX3_1P8	104	44	RTSS_RGMII_MDIO_SPX3
I2S4_DATA1_MDPX3_1P8	105	45	RTSS_RGMII_MDC_SPX3
RTSS_CONN_OSPI0_CS0_SPX3_1P8_N	106	46	RTSS_RGMII_RX_CTL_SPX3
RTSS_CONN_OSPI0_DQS_SPX3_1P8	107	47	RTSS_RGMII_RXC_SPX3
RTSS_CONN_OSPI0_WR_SPX3_1P8_N	108	48	RTSS_RGMII_RXD0_SPX3
RTSS_CONN_OSPI0_CLK_SPX3_1P8	109	49	RTSS_RGMII_RXD1_SPX3
RTSS_CONN_OSPI0_DATA_0_SPX3_1P8	110	50	RTSS_RGMII_RXD2_SPX3
RTSS_CONN_OSPI0_DATA_1_SPX3_1P8	111	51	RTSS_RGMII_RXD3_SPX3
RTSS_CONN_OSPI0_DATA_2_SPX3_1P8	112	52	RTSS_RGMII_TX_CTL_SPX3
RTSS_CONN_OSPI0_DATA_3_SPX3_1P8	113	53	RTSS_RGMII_TXC_SPX3
RTSS_CONN_OSPI0_DATA_4_SPX3_1P8	114	54	RTSS_RGMII_TXD0_SPX3
RTSS_CONN_OSPI0_DATA_5_SPX3_1P8	115	55	RTSS_RGMII_TXD1_SPX3
RTSS_CONN_OSPI0_DATA_6_SPX3_1P8	116	56	RTSS_RGMII_TXD2_SPX3
RTSS_CONN_OSPI0_DATA_7_SPX3_1P8	117	57	RTSS_RGMII_TXD3_SPX3
RTSS_RESOUT_SPX3_1P8_N	118	58	GND
MD_GPIO_47_MDPX3_1P8	119	59	VREG_5P0
MD_GPIO_48_MDPX3_1P8	120	60	VREG_5P0

The following table details the pin mapping for the JEXP3 connector. Table : Pin mapping for the JEXP3 connector

Pin name	Pin number	Pin number	Pin name
MD_GPIO_25_MDPX3_1P8	61	1	EDP2_LN0_P
MD_GPIO_26_MDPX3_1P8	62	2	EDP2_LN0_M
MD_GPIO_27_MDPX3_1P8	63	3	GND
MD_GPIO_28_MDPX3_1P8	64	4	EDP2_LN1_P
MD_RESOUT_MDPX3_1P8_N	65	5	EDP2_LN1_M
MD_GPIO_54_WLAN_EN_1P8	66	6	GND
HST_SW_CTRL_MDPX3_1P8	67	7	EDP2_LN2_P
MD_GPIO_55_BT_EN_1P8	68	8	EDP2_LN2_M
BT0_UART_CTS_MDPX3_1P8	69	9	GND
BT0_UART_RFR_MDPX3_1P8	70	10	EDP2_LN3_P
BT0_UART_TX_MDPX3_1P8	71	11	EDP2_LN3_M
BT0_UART_RX_MDPX3_1P8	72	12	GND
MD_GPIO_10_MDPX3_1P8	73	13	EDP2_AUX_P
SDCARD_DET_MDPX3_1P8_N	74	14	EDP2_AUX_M
BTLE_UART_TX_MDPX3_1P8	75	15	GND
BTLE_UART_RX_MDPX3_1P8	76	16	Not connected
Not connected	77	17	Not connected
GND	78	18	GND
Not connected	79	19	Not connected
Not connected	80	20	Not connected
GND	81	21	GND
Not connected	82	22	Not connected
Not connected	83	23	Not connected
GND	84	24	GND
Not connected	85	25	Not connected
Not connected	86	26	Not connected
GND	87	27	GND
Not connected	88	28	Not connected
Not connected	89	29	Not connected
GND	90	30	MDP_VSYNC_MDPX3_1P8
Not connected	91	31	VREG_5P0_PGOOD
Not connected	92	32	PG_VREG_3P3_SIP
GND	93	33	EDP2_HPD_1P8
PMC_GPIO_4_IPA_PWR_EN_1P8	94	34	Not connected
WLAN_PWR_EN2_1P8	95	35	MD_GPIO_72_MDPX3_1P8
PMC_GPIO_6_WLAN_DBU4_EN_1P8	96	36	DISP_RST_MDPX3_1P8_N
Not connected	97	37	DISP_INT_MDPX3_1P8_N
Not connected	98	38	DES0_LOCK_1P8
IOEXP6_IO_P4_1P8	99	39	LCD_RESET_MDPX3_1P8
SENSOR_I2C_SDA_MDPX3_1P8	100	40	I2C_TO_SPI_MISO_1P8
SENSOR_I2C_SCL_MDPX3_1P8	101	41	I2C_TO_SPI_MOSI_1P8
TX3_DDC_SCL_1P8	102	42	I2C_TO_SPI_CLK_1P8
TX3_DDC_SDA_1P8	103	43	I2C_TO_SPI_CS0_1P8
AUDIO_PRI_SPI_MISO_MDPX3_1P8	104	44	MD_GPIO_41_MDPX3_1P8
AUDIO_PRI_SPI_MOSI_MDPX3_1P8	105	45	MD_GPIO_42_MDPX3_1P8
AUDIO_PRI_SPI_SCLK_MDPX3_1P8	106	46	USB0_VBUS_ON_MDPX3_1P8
AUDIO_PRI_SPI_CS_0_MDPX3_1P8	107	47	IOEXP3_IO_P2_1P8
AUDIO_PRI_SPI_CS_1_MDPX3_1P8	108	48	SENSOR_SLP_CLK_MDPX3_1P8
MD_GPIO_124_MDPX3_1P8	109	49	DISP_I2C_SDA_MDPX3_1P8
MD_GPIO_71_MDPX3_1P8	110	50	DISP_I2C_SCL_MDPX3_1P8
MD_DBG_UART_TX_MDPX3_1P8	111	51	MD_GPIO_80_MDPX3_1P8
MD_DBG_UART_RX_MDPX3_1P8	112	52	MD_GPIO_81_MDPX3_1P8
MD_GPIO_40_MDPX3_1P8	113	53	MD_GPIO_82_MDPX3_1P8
MD_GPIO_39_MDPX3_1P8	114	54	MD_GPIO_83_MDPX3_1P8
PMA_GPIO_02_POFF_COMPLETE_3P3_N	115	55	JEXP3_MD_GPIO_49_MDPX3_1P8
PMA_GPIO_06_AOSS_SLP_ENT_3P3	116	56	JEXP3_MD_GPIO_50_MDPX3_1P8
VREG_WLAN_BT_CORE_VH_1P95	117	57	JEXP3_MD_GPIO_51_MDPX3_1P8
VREG_WLAN_BT_CORE_VL_1P05	118	58	JEXP3_MD_GPIO_52_MDPX3_1P8
VREG_WLAN_BT_CORE_VM_1P35	119	59	CCI_TIMER3_MDPX3_1P8
USB1_VBUS_ON_MDPX3_1P8	120	60	MD_GPIO_64_MDPX3_1P8

The following table details the pin mapping for the JEXP4 connector. Table : Pin mapping for the JEXP4 connector

Pin name	Pin number	Pin number	Pin name
	61	1	SD_CARD_PWR_EN
Not connected	62	2	PCIE1_MEZZCONN_CLK_N
Not connected	63	3	PCIE1_MEZZCONN_CLK_P
Not connected	64	4	GND
Not connected	65	5	PCIE1_MEZZCONN_RX0_N
Not connected	66	6	PCIE1_MEZZCONN_RX0_P
Not connected	67	7	GND
Not connected	68	8	PCIE1_MEZZCONN_RX1_N
Not connected	69	9	PCIE1_MEZZCONN_RX1_P
Not connected	70	10	GND
Not connected	71	11	PCIE1_MEZZCONN_RX2_N
MD_GPIO_63_MDPX3_1P8	72	12	PCIE1_MEZZCONN_RX2_P
PCIE_SWITCH_PWR_EN_1P8	73	13	GND
IOEXP4_IO_P0_1P8	74	14	PCIE1_MEZZCONN_RX3_N
PCIE1_MEZZCONN_RST_1P8_N	75	15	PCIE1_MEZZCONN_RX3_P
PCIE1_MEZZCONN_CLKREQ_1P8_N	76	16	GND
PCIE1_MEZZCONN_WAKE_1P8_N	77	17	PCIE1_MEZZCONN_TX0_N
IOEXP6_IO_P3_1P8	78	18	PCIE1_MEZZCONN_TX0_P
PMA_GPIO_09_USB2_ID	79	19	GND
CCI4_I2C_SDA_MDPX3_1P8	80	20	PCIE1_MEZZCONN_TX1_N
CCI4_I2C_SCL_MDPX3_1P8	81	21	PCIE1_MEZZCONN_TX1_P
IOEXP6_IO_P2_1P8	82	22	GND
Not connected	83	23	PCIE1_MEZZCONN_TX2_N
IOEXP6_IO_P1_1P8	84	24	PCIE1_MEZZCONN_TX2_P
Not connected	85	25	GND
CAM2_PWR_EN_MDPX3_1P8	86	26	PCIE1_MEZZCONN_TX3_N
Not connected	87	27	PCIE1_MEZZCONN_TX3_P
CCI4_I2C_SDA_MDPX3_1P8	88	28	GND
CCI4_I2C_SCL_MDPX3_1P8	89	29	Not connected
CAM2_MCLK_MDPX3_1P8	90	30	Not connected
CAM2_PWDN_MDPX3_1P8	91	31	Not connected
CAM2_STROBE_MDPX3_1P8	92	32	Not connected
CAM2_SPARE_GPIO_MDPX3_1P8	93	33	Not connected
CAM1_PWR_EN_MDPX3_1P8	94	34	Not connected
IOEXP5_IO_P4_1P8	95	35	Not connected
CCI2_I2C_SDA_MDPX3_1P8	96	36	Not connected
CCI2_I2C_SCL_MDPX3_1P8	97	37	Not connected
CAM1_MCLK_MDPX3_1P8	98	38	Not connected
RTSS_PMIC_I2C_SDA_SPX3_1P8	99	39	GND
CAM1_STROBE_MDPX3_1P8	100	40	CSI2_CONN_NC_CLK_P
CAM1_SPARE_GPIO_MDPX3_1P8	101	41	CSI2_CONN_A0_CLK_M
CAM0_PWR_EN_MDPX3_1P8	102	42	CSI2_CONN_B0_LN0_P
IOEXP5_IO_P5_1P8	103	43	CSI2_CONN_C0_LN0_M
CCI0_I2C_SDA_MDPX3_1P8	104	44	CSI2_CONN_A1_LN1_P
CCI0_I2C_SCL_MDPX3_1P8	105	45	CSI2_CONN_B1_LN1_M
CAM0_MCLK_MDPX3_1P8	106	46	CSI2_CONN_C1_LN2_P
RTSS_PMIC_I2C_SCL_SPX3_1P8	107	47	CSI2_CONN_A2_LN2_M
CAM0_STROBE_MDPX3_1P8	108	48	CSI2_CONN_B2_LN3_P
CAM0_SPARE_GPIO_MDPX3_1P8	109	49	CSI2_CONN_C2_LN3_M
GND	110	50	GND
CSI0_CONN_NC_CLK_P	111	51	CSI1_CONN_NC_CLK_P
CSI0_CONN_A0_CLK_M	112	52	CSI1_CONN_A0_CLK_M
CSI0_CONN_B0_LN0_P	113	53	CSI1_CONN_B0_LN0_P
CSI0_CONN_C0_LN0_M	114	54	CSI1_CONN_C0_LN0_M
CSI0_CONN_A1_LN1_P	115	55	CSI1_CONN_A1_LN1_P
CSI0_CONN_B1_LN1_M	116	56	CSI1_CONN_B1_LN1_M
CSI0_CONN_C1_LN2_P	117	57	CSI1_CONN_C1_LN2_P
CSI0_CONN_A2_LN2_M	118	58	CSI1_CONN_A2_LN2_M
CSI0_CONN_B2_LN3_P	119	59	CSI1_CONN_B2_LN3_P
CSI0_CONN_C2_LN3_M	120	60	CSI1_CONN_C2_LN3_M

Debug interface

The platform includes a micro-USB connector receptacle (JTAC, part number: 0475890001) connected to an FTDI chip (U19, part number: FT4232HL-REEL), which is used for debugging purposes. For the location of the debug interface connector on the platform, see the Connectors on Dragonwing IQ-8275 EVK.

JTAG interface

The JTAG connector header on the board is a 20-position pin interconnect with a 0.050” (1.27 mm) pitch and 0.050” (1.27 mm) row spacing. The reference designator for the JTAG connector component is JTAG, and its part number is FTSH-110-01-L-D-RA-K. To use a traditional JTAG connector, an adapter such as the 65-PM339-1 may be required. For the location of the JTAG connectors on the platform, see the Connectors on Dragonwing IQ-8275 EVK.

Audio

For speaker and audio support, the HS0_MI2S interface is used for the two onboard audio amplifiers, and the HS2_MI2S interface is used for the I²S microphone on the mainboard. Both interfaces can optionally be switched to the mezzanine connectors for expansion purposes. Consider the following details about speakers and microphones on the device:

Speakers: Onboard speakers (with MAX98357 I²S-amps); HS0_MI2S is shared between both left and right speakers to enable stereo sound.
Microphones: The EVK includes a single onboard microphone (MMICT5848) that uses the HS2_MI2S interface. By default, the microphone is configured to the left channel.

The following figure shows the audio connections. Figure : Audio connections The following figure shows the Dragonwing IQ-8275 EVK connected to two mini speakers. Figure : Dragonwing IQ-8275 EVK connected to two mini speakers

Introduction

Architecture

Key Documents

Technologies

System

Release Notes

System block diagram

Hardware specification

Exterior view

EVK ports and interfaces

DIP switch

LEDs

Hardware components and interfaces

Processor

Power

Memory

Camera interface

USB interface

DisplayPort (eDP) interface

DSI interface

Storage interfaces

SD card

UFS

EEPROM

On-board sensors

PCIe interface

Flash memory

Expansion headers

Debug interface

JTAG interface

Audio

Next steps

​System block diagram

​Hardware specification

​Exterior view

​EVK ports and interfaces

​DIP switch

​LEDs

​Hardware components and interfaces

​Processor

​Power

​Memory

​Camera interface

​USB interface

​DisplayPort (eDP) interface

​DSI interface

​Storage interfaces

​SD card

​UFS

​EEPROM

​On-board sensors

​PCIe interface

​Flash memory

​Expansion headers

​Debug interface

​JTAG interface

​Audio

​Next steps

System block diagram

Hardware specification

Exterior view

EVK ports and interfaces

DIP switch

LEDs

Hardware components and interfaces

Processor

Power

Memory

Camera interface

USB interface

DisplayPort (eDP) interface

DSI interface

Storage interfaces

SD card

UFS

EEPROM

On-board sensors

PCIe interface

Flash memory

Expansion headers

Debug interface

JTAG interface

Audio

Next steps