Hardware overview
The Qualcomm DragonwingTM IQ-9075 Evaluation Kit (EVK) has the IQ-9075M module. Learn more about the system block diagram, electrical design, features, and capabilities of the EVK.
System block diagram
The following figure shows the system block diagram of the Dragonwing IQ-9075 EVK platform. This figure provides a visual representation of the platform’s architecture, highlighting the main components and their interactions.
../../_images/1-5-iq9-system-block-diagram-03.png
Figure : Dragonwing IQ-9075 EVK system block diagram
Hardware specification
The following table outlines the key hardware specification of the Dragonwing IQ-9075 EVK.
Note
For the list of interfaces supported in this release, see the Qualcomm Linux 2.0 Release Notes.
Table : Dragonwing IQ-9075 EVK key specifications
Interface or feature
Description
SoC
IQ-9075 (part of IQ-9075M)
Memory
6 × 16 bit 36 GB LP5 3200 MHz (3x 12GB LPDDR5) (part of IQ-9075M)
PMIC
4 × PMM8650AU (part of IQ-9075M)
External MCU
Not present
Storage
2 × 128 GB UFS, micro-SD card, EEPROMs for MACs, eMMC on mezzanine card
Display
Four display ports:
2 × mini-DP (one with MST)
2 × DSIs (one to DSI flex, one to expansion)
DSI flex connection with touchscreen
Camera/Video input
4 × Quad deserializers
4 × CSI (C-PHY or D-PHY) cameras
USB
USB0 Type-C (host or device mode)
USB1 Type-C (host mode)
USB2 uUSB 2.0 (host or device mode)
WLAN/Bluetooth®
m.2 module (NFA765A)
2 × printed antennas (Bluetooth shared with one WLAN antenna)
PCIe
Mainboard supported or expanded options (selected through switch):
1 × PCIe x4 slot or expansion (switch)
1 × m.2 E key (WI-Fi) or expansion (switch)
Audio
1 × I2 S mic
2 × I2 S speaker amps
Additional I2 S on GPIOs
Ethernet
RJ45 2.5 GbE MD
CAN/CAN-FD
1 × CAN/CAN-FD on low speed header on mainboard
Low-speed expansion
3.3 V header for developer community with CAN, SPI, I2 C, UART, I2 S
Second low-speed expansion
QUPs and GPIOs on mezzanine connectors
Sensors
IMU: ICM-42688
QUPs on expansion
Trusted platform module (TPM)
ST33HTPH2x32AHE4 on mainboard
Exterior view
The following figures show the exterior of the Dragonwing IQ-9075 EVK with the bottom case.
../../_images/1-5-exterior-evk-top-view-and-with-casing.png
Figure : Exterior view of the EVK with bottom case
The following figures show the side views of the Dragonwing IQ-9075 EVK, with labeled ports, connectors, and switches.
../../_images/iq9-views.png
The following figure shows the top view of the core board.
../../_images/1-5-1-iq9-top-view.png
Figure : Top view of the core board
EVK ports and interfaces
The following figure shows a detailed view of all the connectors on the Dragonwing IQ-9075 EVK.
../../_images/1-5-iq9-top-view.png
Figure : Connectors on Dragonwing IQ-9075 EVK
The following figure shows the platform with few cables plugged in.
../../_images/1-5-iq9-with-cables.png
Figure : Platform with cables plugged in
Table : Connectors and functions
Connectors
Functions
JPWR
DC power (barrel connector) plug, 12 V–36 V input voltage
JLS1
Low speed IO header receptacle (LS1)
SW1
8 position surface mount DIP switch
SW2
4 position surface mount DIP switch
SW3
6 position surface mount DIP switch
JCAM0
MIPI CSI0 camera interconnect receptacle
JCAM1
MIPI CSI1 camera interconnect receptacle
JCAM2
MIPI CSI2 camera interconnect receptacle
JCAM3
MIPI CSI3 camera interconnect receptacle
JPCIE
PCI Express v4 receptacle connector (PCIe1)
JEDP1
EDP1 connector
JEDP0
EDP0 connector
JETH
Ethernet connector (2.5 GbE)
JUSB1
USB-C (USB Type-C) receptacle connector for USB1
JUSB0
USB-C (USB Type-C) receptacle connector for USB0
JUSB2
Micro-USB receptacle for USB2
JRST
Tactile switch for system reset (initiates graceful shutdown)
J13
Antenna for WLAN
S4
Slide switch for power or automation control
JDISP
Connector for DSI display
JTAC
Micro-USB receptacle for debug UART
JTAG
Header connector for JTAG
J14
Antenna for WLAN/Bluetooth
JEXP1–JEXP4
Board-to-board 120 position connector receptacle
DIP switch
The following images show the location of the DIP switches on the mainboard.
../../_images/1-5-iq9-dip-switches-2.png
Figure : DIP switches 1, 2, and 3 on Dragonwing IQ-9075 EVK
../../_images/1-5-1-dip-switches-4-7-8-9.png
Figure : DIP switches 4, 7, 8, and 9 on Dragonwing IQ-9075 EVK
Note
If a DIP switch is facing up, it indicates that the switch is on.
The following table details DIP switch operations for the Dragonwing IQ-9075 EVK, including functions and settings for board configuration.
Table : DIP switch position and its respective functions
Switch
Connection when ON
Connection when OFF (default from factory)
Notes
SW1-1
PCIe0 is routed to mezzanine
PCIe0 is connected to the mainboard Wi-Fi module
SW1-2
PCIe1 is routed to mezzanine
PCIe1 is connected to the mainboard PCIe connector
SW1-3
SDIO is routed to mezzanine
SDIO is routed to the mainboard SD card
SW1-4
DSI is routed to mainboard flex connector
DSI is routed to mezzanine
SW1-5
CSI0 is routed to mezzanine
CSI0 is routed to the mainboard CSI flex connector
SW1-6
CSI1 is routed to mezzanine
CSI1 is routed to the mainboard CSI flex connector
SW1-7
CSI1 is routed to mezzanine
CSI2 is routed to the mainboard CSI flex connector
SW1-8
CSI2 is routed to mezzanine
CSI3 is routed to the mainboard CSI flex connector
SW2-1
Main domain forced USB boot/EDL
No impact
Currently, this switch isn’t enabled in software.
SW2-2
Main domain fast boot
No impact
SW2-3
Main domain and Sail domain forced USB boot/EDL (combined)
No impact
Currently, the software implementation puts both domains into EDL mode together. It’s important for software download.
SW2-4
Sail domain Fastboot mode
No impact
SW3-1
OSPI is routed to mezzanine
OSPI is connected to onboard memory for MCU
SW3-2
Force MD and MCU PS_HOLD
No impact
SW3-3
Watchdog is disabled
RAM dump is enabled
SW3-4
Boot from eMMC
Boot from UFS
eMMC located on interface and mezzanine
SW3-5
EUD enable
No impact
SW3-6
Skip MD BIST
No impact
SW4-1
Reserved for internal use
Don’t change.
SW7-1
Reserved for internal use
Don’t change.
SW8-1
Reserved for internal use
Don’t change.
SW9-1
Reserved for internal use
Don’t change.
LEDs
The Dragonwing IQ-9075 EVK has status LEDs that monitor system functions such as power-on and board faults, crucial for debugging and bringup. The following table lists and summarizes the functions of the LEDs. The Connectors on Dragonwing IQ-9075 EVK shows the location and the LEDs present on the board.
Table : Summary of reference designator, location, color, and function of LEDs
Reference designator
Location
Color
Function
DS1
Mainboard
Green
Reserved for debugging
DS8
Mainboard
Green
Ethernet status LEDs
DS9
Mainboard
Green
DS10
Mainboard
Green
VREG_3P3_SIP indicator
DS11
Mainboard
Orange
VREG_3P3_SIP indicator
LED1
Mainboard
RGB
Software-controlled RGB lighting through GPIOs
Hardware components and interfaces
Review the following high-level details of Dragonwing IQ-9075 processor, power supply, memory, and various interfaces, such as camera, USB, and DisplayPort. It also includes sensors, flash memory, expansion options, a debug interface, audio support, thermal management, fan control, and accessory boards.
Processor
The target processor used in the Dragonwing IQ-9075 EVK is the Dragonwing IQ-9075 SoC, also known as the IQ-9075. This SoC features an octa-core Kryo™ Gen 6 CPU built on Arm v8.2 Cortex technology, with clock support up to 2.55 GHz.
In addition to the eight high-performance CPU cores, the SoC includes a GPU and two Hexagon Tensor Processors with vector and matrix extensions, enabling the management of various concurrent compute and AI workloads simultaneously. The SoC offers extensive peripheral support, including integrated Ethernet, USB, Wi-Fi, PCIe, and Bluetooth. It’s capable of delivering up to 100 INT8 TOPS, making it suitable for powering high-performance, AI-centric, and Edge AI industrial use cases.
The target applications include:
Factory automation
Industrial robots
Industrial personal computers
Drones
Edge AI Boxes
Machine Vision
Autonomous Mobile Robots (AMRs)
Industrial gateways
The IQ-9075 SoC is integrated within the IQ-9075M module, which also houses the four PMICs and three LPDDR5 SD RAM memory components. The following figure shows the IQ-9075 SoC within IQ-9075M module.
../../_images/1-5-1-iq9-soc-module.png
Figure : IQ-9075 SoC within IQ-9075M module
Power
The main power input to the Dragonwing IQ-9075 board is provided through the 2.10 mm barrel jack connector (JPWR, JACK-C-PC-10A-RA(R)), supporting an input voltage range of 12 V to 36 V. The EVK also includes a Type-C to barrel plug adapter. Four power management ICs manage the respective power supplies to various system blocks, including the SoC, PMIC, PCIe, and expansion ports.
The following figure shows the four PMICs on the IQ-9075M module.
../../_images/1-5-1-iq9-pmic.png
Figure : Four PMICs on the IQ-9075M module
Memory
The IQ-9075M module has three 12 GB LPDDR5 SDRAM ICs. The following figure shows the LPDDR5 memory ICs on the module.
../../_images/1-5-1-iq9-memory.png
Figure : LPDDR5 memory on the IQ-9075M module
Camera interface
An analog switch is used for each MIPI CSI interface, allowing the MIPI CSI interfaces to be accessible through both the JCAM camera interconnect receptacle and the B2B expansion connector (JEXP4).
For more information about camera mezzanine board, see the Qualcomm Dragonwing IQ-9075 PVT GMSL Mezzanine Interface User Guide.
The following table lists the CSI interfaces, their analog switch, camera connector, and B2B connector pinout.
Note
You can connect the CSI interfaces to the mainboard connector or to GMSL mezzanine through a DIP switch setting. For the correct setting, see the Table: DIP switch position and its respective functions.
Table : CSI settings
CSI interface
Analog switch
Camera connector
B2B connector pinout
CSI0
U45
(TMUX646ZECR)
JCAM0
JEXP4, Pins 111-120
CSI1
U42
(TMUX646ZECR)
JCAM1
JEXP4, Pins 51-60
CSI2
U44
(TMUX646ZECR)
JCAM2
JEXP4, Pins 40-49
CSI3
U43
(TMUX646ZECR)
JCAM3
JEXP4, Pins 29-38
The four MIPI CSI ports can operate in either C-PHY or D-PHY mode. They support a range of existing cameras and flexes, including the OV9282 and IMX577.
To use a GMSL camera with the Dragonwing IQ-9075 EVK, connect it through the GMSL mezzanine, which must be ordered separately. The CSI ports are routed through the DIP switches, allowing configuration and setup.
Note
Four cameras have been validated concurrently, which includes two YUV GMSL cameras connected to GMSL Port2 and Port3, and two MIPI camera connected to MIPI CSI0 and CSI1 slots.
The following figure shows the Dragonwing IQ-9075 EVK with different camera configurations.
../../_images/evk-with-gmsl-mezzanine-attached-csi-camera-rpi-adapter.png
Figure : Dragonwing IQ-9075 EVK with (L) GMSL mezzanine attached; (R) MIPI CSI cameras
The following figure shows the camera interfaces and configuration.
IQ-9075M SoC
U7
SW1
DIPswitch
JEXP4
JCAM0
CSI0 CLK/LNx
GPIO_60
CCI0_I2C_SDA_MDPX3_1P8
CCI0_I2C_SCL_MDPX3_1P8
CAM0_MCLK_MDPX3_1P8
GPIO_61
GPIO_72
U45
AB switch
SEL
Dx
SxA
SxB
CSI0 CLK/LNx
CSI0 CLK/LNx
CSI0 CLK/LNx
CAM0_DIP_SW
JEXP4
JCAM1
CSI1 CLK/LNx
GPIO_62
CCI2_I2C_SDA_MDPX3_1P8
CCI2_I2C_SCL_MDPX3_1P8
CAM1_MCLK_MDPX3_1P8
GPIO_63
GPIO_73
U42
AB switch
SEL
Dx
SxA
SxB
CSI1 Data
CSI1 CLK/LNx
CSI1 CLK/LNx
CAM1_DIP_SW
JEXP4
JCAM2
CSI2 CLK/LNx
GPIO_64
CCI4_I2C_SDA_MDPX3_1P8
CCI4_I2C_SCL_MDPX3_1P8
CAM2_MCLK_MDPX3_1P8
GPIO_65
GPIO_74
U44
AB switch
SEL
Dx
SxA
SxB
CSI2 Data
CSI2 CLK/LNx
CSI2 CLK/LNx
CAM2_DIP_SW
JEXP4
JCAM3
CSI3 signals
GPIO_66
CCI6_I2C_SDA_MDPX3_1P8
CCI6_I2C_SCL_MDPX3_1P8
CAM2_MCLK_MDPX3_1P8
GPIO_67
GPIO_75
U43
AB switch
SEL
Dx
SxA
SxB
CSI3 Data
CSI3 CLK/LNx
CSI3 CLK/LNx
CAM3_DIP_SW
Third-party
Connectors
Primary interfacesignals
Control / Power/ Auxiliary signals
Qualcomm
Figure : Camera interfaces and configuration
USB interface
The board features three USB connectors: two Type-C connectors (USB0 and USB1) and one micro-USB connector (USB2). The following table outlines the USB properties of the board. Connectors on Dragonwing IQ-9075 EVK shows the location of the USB connectors on the board.
Table : Reference designator, USB interface and type
Reference designator
USB interface and type
Description
JUSB0
USB0 USB-C (USB Type-C)
USB 3.1 Gen 2, HS + SS, supports host or device mode
JUSB1
USB1 USB-C (USB Type-C)
USB 3.1 Gen 2, HS + SS, supports host mode
JUSB2
USB2 Micro-USB
USB2.0, HS, supports host modes
The following figure shows the USB interfaces and configuration.
IQ-9075M SoC
U7L
JUSB0
USB Type Cconnector(USB0)
JUSB1
USB Type Cconnector(USB1)
JUSB2
Micro USBconnector(USB2)
USB0 SS
USB0 HS
PME_GPIO_4
GPIO_50
GPIO_48/49
PME_GPIO_5
U91
Port controller
USB_VBUS
I2C addr: 0x67
Port controller
USB_VBUS
I2C addr: 0x47
U110
U111
U92
U69
(blue wire)
I2C_SDA/SCL
Voltage divider
Voltage divider
EN
(blue wire)
EN
5V supply(for host mode)
5V supply(for host mode)
U6
5 V supply(for host mode)
GPIO expander
GPIO_95/96
GPIO_19
GPIO_81
GPIO_80
USB1 HS/SS
PME_GPIO_6
GPIO_51
VREG_5P0
ID driven low if downstreamdevice connected
VREG_3P3_SIP
VREG_MDPX3_1P8
USB0 SS
USB1 HS/SS
USB SS
USB0 HS
USB HS
USB2_ID
USB2 HS
USB0 SS
USB0_ID
I2C_SDA/SCL
INT_N
VREG_5P0
VREG_3P3_SIP
VREG_MDPX3_1P8
FAULT_N
No connect
FAULT_N
No connect
INT_N
FAULT_N
USB0_VBUS
From connector(device mode)or into connector(host mode)
USB1_ID
I2C_SDA/SCL
I2C_SDA/SCL
PMC_GPIO_10
PMC_GPIO_9
PME_GPIO_11
USB2 HS
FAULT_N
EN
INT_N
CC1/CC2
USB SS
CC1/CC2
USB2_VBUS
From connector(device mode)or into connector(host mode)
USB1_VBUS
Into connector(host mode only)
Third-party
Connectors
Primary interfacesignals
Control / Power/ Auxiliary signals
Qualcomm
ID driven low if downstreamdevice connected
I2Caddr:0x39
U103
GPIO expander
I2Caddr:0x3b
P2
P3
P3
P5
U40
USB hub
USB_VBUS_DET
USB_RESET_N
I2C
I2C addr: 0x25
USB interfaces and configuration
DisplayPort (eDP) interface
The target processor is equipped with four eDP interfaces. EDP0 and EDP1 are routed to the DP connector receptacles JEDP0 and JEDP1, respectively.
For the location of the DP connectors on the platform, see the Connectors on Dragonwing IQ-9075 EVK.
Table : eDP interface connections
eDP interface
Connected to
EDP0
JEDP0 (DP3AR020SU32JQ1R400)
EDP1
JEDP1 (DP3AR020SU32JQ1R400)
The following figure shows the eDP interfaces and configuration.
IQ-9075M SoC
U7
DP connector3VT11207-N730-7H(ESD protected)
JEDP0
DP connector3VT11207-N730-7H(ESD protected)
JEDP1
120-pin B2Bexpansionconnector
JEXP3
EDP0 AUX/LNx
GPIO_101
EDP0 AUX/LNx
EDP0_HPD_MDPX3_1P8
EDP1 AUX/LNx
GPIO_102
EDP2 AUX/LNx
EDP3 AUX/LNx
GPIO_103
GPIO_104
EDP1 AUX/LNx
EDP1_HPD_MDPX3_1P8
EDP2 AUX/LNx
EDP3 AUX/LNx
EDP2_HPD_MDPX3_1P8
EDP3_HPD_MDPX3_1P8
Connectors
Primary interfacesignals
Control / Power/ Auxiliary signals
Qualcomm
eDP interfaces and configuration
DSI interface
The IQ-9075 processor supports two 4-lane MIPI-DSI with VESA DSC v1.2.
The Dragonwing IQ-9075 EVK uses an analog switch for DSI0 interface, allowing the interface to be accessible through both the JDISP LCD receptacle and the B2B expansion connector (JEXP1).
Note
Due to the analog switch, you can connect the DSI0 interfaces to the mainboard LCD connector or to the GMSL mezzanine through a DIP switch setting. For the intended DSI setting, see the Table: DIP switch position and its respective functions.
The software support for DSI interface will be provided in a future release.
The following figure shows DSI interfaces and configuration.
IQ-9075M SoC
U7
SW1
DIPswitch
120-pin B2Bexpansionconnector
JEXP3
Displayconnector
JDISP
JEXP3
DSI0 CLK/LNx
GPIO_24
DISP_I2C_SDA_MDPX3_1P8
DISP_I2C_SCL_MDPX3_1P8
TOUCH_INT_MDPX3_1P8_N
GPIO_25
GPIO_72
U46
AB switch
SEL
Dx
SxA
SxB
DSI0 CLK/LNx
DSI0 CLK/LNx
DSI0 CLK/LNx
DSI0_DIP_SW
120-pin B2Bexpansionconnector
DSI1 CLK/LNx
DSI1 CLK/LNx
DSI0-1 routed differentially in D-PHY mode
Third-party
Connectors
Primary interfacesignals
Control / Power/ Auxiliary signals
Qualcomm
Figure : DSI interfaces and configuration
Storage interfaces
The Dragonwing IQ-9075 device has three types of storage interfaces: secure digital (SD) card, universal flash storage (UFS), and electrically erasable programmable read-only memory (EEPROM).
SD card
The target processor supports a single SDIO interface (SDC1). The SDC pins are routed through analog switches (U2, U3) to facilitate connections through the micro SD card connector (JSDC) on the board, and through the expansion connector (JEXP4, pins 61–71) for eMMC connectivity on a mezzanine board.
Note
You can connect the SDIO to the mezzanine or the micro SD card through a DIP switch setting. For the correct setting, see the Table: DIP switch position and its respective functions.
The following table lists the SDC interfaces on the board.
Table: SDC interfaces
SDC interface
Analog switch
uSD connector
B2B connector pinout
SDC1
U2, U3 (PI3A27518ZDEX_QFN24P)
JSDC
JEXP4, pins 61-71
The following figure shows the SD card interfaces and configuration.
IQ-9075M SoC
U7K
SW1
JSDC
SW1
JEXP4
DIPswitch
120-pin B2Bexpansionconnector
MICRO SD cardconnector(ESD protected)
GPIO_36
SDC1 CLK/CMD/DATA[0:3]
SDC1 RCLK/DATA[4:7]
SDC CLK/CMD/DATA[0:4]
U2
U119
6-channel, 1:2multiplexer/demultiplexer
Voltage level translatorwith EMI filter andESD protection
IN1
COMx
NCx
NOx
SDC RCLK/DATA[4:7]
U3
6-channel, 1:2multiplexer/demultiplexer
IN1
COMx
NCx
NOx
SDC CLK/CMD/DATA[0:4]
SDC CLK/CMD/DATA[0:4]
SDC CLK/CMD/DATA[0:4]
SDC RCLK/DATA[4:7]
SDIO_MUX_SEL
SDIO_MUX_SEL
SDCARD_DET_MDPX3_1P8_N
Third-party
Connectors
Primary interfacesignals
Control / Power/ Auxiliary signals
Qualcomm
SD card interfaces and configuration
Note
Additional components on eMMC signals may negatively impact signal integrity, potentially leading to boot failures. The existing circuitry isn’t optimal and shouldn’t be replicated. For the best performance and higher speed support, a cleaner layout is recommended.
UFS
The target processor supports two UFS 3.1 Gear 4 interfaces, each with two lanes for on-board memory. UFS0 serves as the main domain boot-up device. The Dragonwing IQ-9075 EVK platform is equipped with two 128 GB UFS devices on the mainboard.
The following table lists the part numbers and manufacturers of these UFS devices.
Table : Part numbers and manufacturers of UFS devices
Reference designator
Interface identifier
MPN
Manufacturer
Description
U38
UFS0
THGJFGT0T25BAB8
KIOXIA AMERICA INC
128 GB UFS3.1 (Gear4) Q100-GR2 RoHS
U39
UFS1
The following figure shows the UFS interfaces and configuration.
IQ-9075M SoC
U7K
U38
Switches
UFS0 REFCLK/RESET/DATA
UFS0 REFCLK/RESET/DATA
Flash memory128 GB
THGJFGT0T25BAB8
U39
UFS1_VCC
UFS1_VCCQ
UFS1_VCCQ2
UFS1 REFCLK/RESET/DATA
UFS1 REFCLK/RESET/DATA
Flash memory128 GB
THGJFGT0T25BAB8
UFS0_VCC
UFS0_VCCQ
UFS0_VCCQ2
Primary interfacesignals
Control / Power/ Auxiliary signals
Third-party
Qualcomm
UFS interfaces and configuration
EEPROM
The Dragonwing IQ-9075 EVK platform has a single EEPROM device dedicated to storing MAC addresses for Ethernet, Wi-Fi, and Bluetooth.
The following table lists the part number and manufacturer of the EEPROM device.
Table : Part number and manufacturer of the EEPROM device
Reference designator
Device
MPN
Manufacturer
Description
U20
EEPROM
93LC46B-I/SN
Microchip Technology Inc.
1 Kbit low-voltage serial electrically erasable PROMs (EEPROM)
On-board sensors
The Dragonwing IQ-9075 EVK platform includes an on-board IMU and a temperature sensor. They are connected to the real-time subsystem (RTSS) domain of IQ-9075 EVK.
Note
Currently, the software doesn’t support the IMU and temperature sensors.
The following table lists the part numbers and manufacturers of these sensors.
Table : Part numbers and manufacturers of the sensors
Reference designator
Sensor type
Communication protocol used
MPN
Manufacturer
U97
IMU sensor
I2C
ICM-42688
TDK InvenSense
U109
Temperature sensor
SPI
TMP411DQDGKRQ1
Texas Instruments
PCIe interface
The target processor supports two PCIe interfaces: PCIe0 and PCIe1. PCIe0 is Gen4 2-lane and PCIe1 is Gen4 4-lane PCIe interface.
Both PCIe interfaces are connected to an A/B switch, which by default, connects them to the expansion mezzanine. Configure the DIP switches to connect the PCIe0 to the Wi-Fi/Bluetooth module and PCIe1 to the full size PCIe x4 connector on the mainboard. For DIP switch settings, see the Table: DIP switch position and its respective functions.
For more information about the mezzanine board, see the Qualcomm Dragonwing IQ-9075 PVT IFP Mezzanine Board User Guide.
The following figure shows the PCIe interfaces and configuration.
IQ-9075M SoC
U7
SW1
JBTWL
JPCIE
S6, U15, U16, U17
DIPswitch
PCIe x4connector
120-pin B2Bexpansionconnector
JEXP4
JEXP1
M.2 connectorfor Wi-Fi/BTmodule
Switches
S6: GPIO_3 to GPIO_5U15, U16, U17: REFCLK, TX, RX
PCIE0 CLK/TX/RX
GPIO_0
PCIE0_WAKE
PCIE0_CLKREQ
PCIE0_RST
GPIO_1
GPIO_2
S5, U10, U11, U12
Switches
S5: GPIO_0 to GPIO_2U10, U11, U12: REFCLK, TX, RX
SEL
PCIE0 CLK/TX/RX
PCIE0 CLK/TX/RX
PCIE0 GPIOs
PCIE0 CLK/TX/RX
PCIE0 GPIOs
PCIE1 CLK/TX/RX
PCIE1 GPIOs
PCIE1 CLK/TX/RX
PCIE1 GPIOs
PCIE1 CLK/TX/RX
GPIO_3
PCIE1_CLKREQ
PCIE1_RST
PCIE1_WAKE
GPIO_4
GPIO_5
SEL
PCIE1 CLK/TX/RX
PCIE1_MUX_SEL
PCIE0_MUX_SEL
120-pin B2Bexpansionconnector
Third-party
Connectors
Primary interfacesignals
Control / Power/ Auxiliary signals
Qualcomm
Figure : PCIe interfaces and configuration
Flash memory
The Dragonwing IQ-9075 EVK uses OSPI interface to support 2GBIT flash memory. The analog switch for OSPI interface allows the interface to be accessible through both the flash memory device and the B2B expansion connector (JEXP2).
Note
Due to the analog switch, you can connect the OSPI to the memory device or to B2B connector through DIP switch settings. For the intended OSPI settings, see the Table: DIP switch position and its respective functions.
The following figure shows the flash memory interfaces and configuration.
IQ-9075M SoC
U7
SW3
U41
DIPswitch
NOR flash memory
120-pin B2Bexpansionconnector
JEXP2
SAIL_IO_71 to 78
SAIL_IO_67
OSPI0_CS0
OSPI0_DQS
OSPI0_WR
Test point(TP35)
SAIL_IO_68
SAIL_IO_68
S7, S8, S9
A/B switches
SEL
Dx
SxA
SIOx
SxB
OSPI0_DATA[0:7]
OSPI0_DATA[0:7]
VREG_SPX3_1P8
Flash GPIOs
OSPI0_DATA[0:7]
Flash GPIOs
OSPI_MUX_SEL
Third-party
Connectors
Primary interfacesignals
Control / Power/ Auxiliary signals
Qualcomm
Figure : Flash memory interfaces and configuration
The following figures show controller area network (CAN) block diagram and interfaces.
IQ-9075M SoC
Voltage leveltranslator(TXB0108NMER)
CAN device
CAN
RTSS_IO_38
RTSS_IO_37
QUP SE4with SPI
B3
B2
B1
B4
RTSS_IO_5
A4
RTSS_IO_4
A3
RTSS_IO_2
A2
RTSS_IO_3
TLE9255WLC
A1
VCCB
VCCA
CSN
SCLK
MISO
MOSI
RXD
VCC
5 V
3.3 V
1.8 V
12 V
3.3 V
VBAT
VIO
TXD
CANL
CANH
CANL
CANH
WAKE
Qualcomm
Figure : CAN0 interfaces
IQ-9075M SoC
CAN device
CAN
RTSS_CAN_RX
RTSS_CAN_TX
ADM3058EBRIZ-RL
RXD
VDD1
1.8 V
5 V
VDD2
TXD
CANL
CANH
CANL
60.4 kΩ
4.7 nF
60.4 kΩ
CANH
Qualcomm
Figure : CAN1 to CAN7 interfaces
Expansion headers
The Dragonwing IQ-9075 EVK features four high-speed expansion connectors (JEXP1-4, 10139781-121422LF). Connect accessory cards such as GMSL mezzanine and RBx adapters to these connectors. Additionally, other interfaces mentioned throughout this document are also routed to these connectors. For the position of the connectors, see the Connectors on Dragonwing IQ-9075 EVK.
For more information about the mezzanine board, see the Qualcomm Dragonwing IQ-9075 PVT IFP Mezzanine Board User Guide.
The following table details the pin mapping for the JEXP1 connector.
Table : Pin mapping for the JEXP1 connector
Pin name
Pin number
Pin number
Pin name
GND
61
1
VREG_SYSTEM_PWR
DSI0_A0_LN0_P_CONN
62
2
VREG_SYSTEM_PWR
DSI0_B0_LN0_M_CONN
63
3
VREG_SYSTEM_PWR
GND
64
4
VREG_SYSTEM_PWR
DSI0_C0_LN1_P_CONN
65
5
VREG_SYSTEM_PWR
DSI0_A1_LN1_M_CONN
66
6
GND
GND
67
7
GND
DSI0_B1_CLK_P_CONN
68
8
GND
DSI0_C1_CLK_M_CONN
69
9
GND
GND
70
10
VREG_3P3_SIP
DSI0_A2_LN2_P_CONN
71
11
VREG_3P3_SIP
DSI0_B2_LN2_M_CONN
72
12
GND
GND
73
13
GND
DSI0_C2_LN3_P_CONN
74
14
PME_GPIO_3_USB1_FAULT_3P3_N
DSI0_NC_LN3_M_CONN
75
15
PME_GPIO_4_USB0_FAULT_3P3_N
GND
76
16
MD_GPIO_17_MDPX3_1P8
VREG_L7C_1P8
77
17
MD_GPIO_18_MDPX3_1P8
GND
78
18
SGMII0_MDC_MDPX3_1P8
VREG_MDPX3_1P8
79
19
SGMII0_MDIO_MDPX3_1P8
GND
80
20
SGMII0_CONN_RX_P
IOEXPAN1_INT_MDPX3_1P8_N
81
21
SGMII0_CONN_RX_M
STR_WAKE_MDPX3_1P8
82
22
SGMII0_CONN_TX_P
SGMII1_RX_P
83
23
SGMII0_CONN_TX_M
SGMII1_RX_M
84
24
SGMII0_INT_MDPX3_1P8_N
SGMII1_TX_P
85
25
SGMII0_RST_MDPX3_1P8_N
SGMII1_TX_M
86
26
MD_GPIO_13_MDPX3_1P8
SGMII1_INT_MDPX3_1P8_N
87
27
MD_GPIO_14_MDPX3_1P8
SGMII1_RST_MDPX3_1P8_N
88
28
MD_GPIO_15_MDPX3_1P8
SAIL_ERR0_SPX3_1P8
89
29
MD_GPIO_16_MDPX3_1P8
SAIL_ERR1_SPX3_1P8
90
30
SAIL_CAN0_TX_SPX3_1P8
SAIL_SPI_MISO_SPX3_1P8
91
31
SAIL_CAN0_RX_SPX3_1P8
SAIL_SPI_MOSI_SPX3_1P8
92
32
SAIL_CAN1_TX_SPX3_1P8
SAIL_SPI_SCLK_SPX3_1P8
93
33
SAIL_CAN1_RX_SPX3_1P8
SAIL_SPI_CS_0_SPX3_1P8
94
34
SAIL_CAN2_TX_SPX3_1P8
SAIL_SPI_CS_1_SPX3_1P8
95
35
SAIL_CAN2_RX_SPX3_1P8
SAIL_GPIO_15_SPX3_1P8
96
36
SAIL_CAN3_TX_SPX3_1P8
SAIL_GPIO_16_SPX3_1P8
97
37
SAIL_CAN3_RX_SPX3_1P8
SAIL_GPIO_17_SPX3_1P8
98
38
SAIL_CAN4_TX_SPX3_1P8
SAIL_GPIO_18_SPX3_1P8
99
39
SAIL_CAN4_RX_SPX3_1P8
SAIL_PMIC_INT_SPX3_1P8_N
100
40
SAIL_CAN5_TX_SPX3_1P8
SAIL_INT_SPX3_1P8_N
101
41
SAIL_CAN5_RX_SPX3_1P8
SAIL_PWR_READY_SPX3_1P8
102
42
SAIL_CAN6_TX_SPX3_1P8
SAIL_SLP_EN_SPX3_1P8
103
43
SAIL_CAN6_RX_SPX3_1P8
SAIL_DBG_UART_TX_SPX3_1P8
104
44
SAIL_CAN7_TX_SPX3_1P8
SAIL_DBG_UART_RX_SPX3_1P8
105
45
SAIL_CAN7_RX_SPX3_1P8
GND
106
46
SAIL_CAN_INT0_SPX3_1P8
PCIE0_MEZZCONN_CLK_P
107
47
SAIL_CAN_INT1_SPX3_1P8
PCIE0_MEZZCONN_CLK_N
108
48
SAIL_CAN_STB_0_SPX3_1P8
GND
109
49
SAIL_CAN_STB_1_SPX3_1P8
PCIE0_MEZZCONN_RX0_P
110
50
SAIL_CAN_STB_2_SPX3_1P8
PCIE0_MEZZCONN_RX0_N
111
51
SAIL_CAN_STB_3_SPX3_1P8
GND
112
52
SAIL_CAN6_CTL_SPX3_1P8
PCIE0_MEZZCONN_RX1_P
113
53
SAIL_CAN7_CTL_SPX3_1P8
PCIE0_MEZZCONN_RX1_N
114
54
SAIL_CAN8_CTL_SPX3_1P8
GND
115
55
PCIE0_MEZZCONN_RST_1P8_N
PCIE0_MEZZCONN_TX0_P
116
56
PCIE0_MEZZCONN_CLKREQ_1P8_N
PCIE0_MEZZCONN_TX0_N
117
57
PCIE0_MEZZCONN_WAKE_1P8_N
GND
118
58
PMG_GPIO_3_GNSS_RESET_1P8
PCIE0_MEZZCONN_TX1_P
119
59
PMG_GPIO_4_GNSS_EN_1P8
PCIE0_MEZZCONN_TX1_N
120
60
PMG_GPIO_5_GNSS_BOOT_MODE_1P8
The following table details the pin mapping for the JEXP2 connector.
Table : Pin mapping for the JEXP2 connector
Pin name
Pin number
Pin number
Pin name
VREG_MDPX3_1P8
61
1
VREG_SPX3_1P8
GND
62
2
GND
SOC_MI2S_MCLK0_MDPX3_1P8
63
3
VREG_SPX8
SOC_MI2S1_SCK_MDPX3_1P8
64
4
GND
SOC_MI2S1_WS_MDPX3_1P8
65
5
USB01_I2C_SDA_MDPX3_1P8
SOC_MI2S1_DATA0_MDPX3_1P8
66
6
USB01_I2C_SCL_MDPX3_1P8
SOC_MI2S1_DATA1_MDPX3_1P8
67
7
VREG_1P8_EN
MI2S2_SCK_MDPX3_1P8
68
8
VREG_1P2_EN
MI2S2_WS_MDPX3_1P8
69
9
USB_VBUS_DET_MDPX3_1P8
MI2S2_DATA0_MDPX3_1P8
70
10
USB_RESET_MDPX3_1P8_N
MI2S2_DATA1_MDPX3_1P8
71
11
USB1_ID_MDPX3_1P8
HS0_MI2S_SCK_CONN
72
12
USB0_ID_MDPX3_1P8
HS0_MI2S_WS_CONN
73
13
PMG_GPIO_8
HS0_MI2S_DATA0_CONN
74
14
PME_GPIO_7_SENSOR_RST_1P8
HS0_MI2S_DATA1_CONN
75
15
PME_GPIO_6_USB1_INT_3P3_N
HS1_MI2S_SCK_CONN
76
16
PME_GPIO_5_USB0_INT_3P3_N
HS1_MI2S_WS_CONN
77
17
MD_GPIO_70_MDPX3_1P8
HS1_MI2S_DATA0_CONN
78
18
EXP_I2C_SDA_MDPX3_1P8
HS1_MI2S_DATA1_CONN
79
19
EXP_I2C_SCL_MDPX3_1P8
HS2_MI2S_SCK_CONN
80
20
FAN_INT_MDPX3_1P8_N
HS2_MI2S_WS_CONN
81
21
HUB_P2_USB_HS_P
HS2_MI2S_DATA0_CONN
82
22
HUB_P2_USB_HS_M
HS2_MI2S_DATA1_CONN
83
23
HUB_P2_USB_SS_RX_P
SOC_QUA_MI2S_SCK_MDPX3_1P8
84
24
HUB_P2_USB_SS_RX_M
SOC_QUA_MI2S_WS_MDPX3_1P8
85
25
HUB_P2_USB_SS_TX_P
SOC_QUA_MI2S_DATA0_MDPX3_1P8
86
26
HUB_P2_USB_SS_TX_M
SOC_QUA_MI2S_DATA1_MDPX3_1P8
87
27
GND
SOC_QUA_MI2S_DATA2_MDPX3_1P8
88
28
HUB_P3_USB_HS_M
SOC_QUA_MI2S_DATA3_MDPX3_1P8
89
29
HUB_P3_USB_HS_P
SOC_I2S1_SCK_MDPX3_1P8
90
30
HUB_P3_USB_SS_TX_P
SOC_I2S1_WS_MDPX3_1P8
91
31
HUB_P3_USB_SS_TX_M
SOC_I2S1_DATA0_MDPX3_1P8
92
32
HUB_P3_USB_SS_RX_P
SOC_I2S1_DATA1_MDPX3_1P8
93
33
HUB_P3_USB_SS_RX_M
I2S2_CLK_MDPX3_1P8
94
34
GND
I2S2_WS_MDPX3_1P8
95
35
HUB_P4_USB_HS_M
I2S2_DATA0_MDPX3_1P8
96
36
HUB_P4_USB_HS_P
I2S2_DATA1_MDPX3_1P8
97
37
HUB_P4_USB_SS_TX_P
SOC_I2S3_SCK_MDPX3_1P8
98
38
HUB_P4_USB_SS_TX_M
SOC_I2S3_WS_MDPX3_1P8
99
39
HUB_P4_USB_SS_RX_P
SOC_I2S3_DATA0_MDPX3_1P8
100
40
HUB_P4_USB_SS_RX_M
SOC_I2S3_DATA1_MDPX3_1P8
101
41
GND
I2S4_SCK_MDPX3_1P8
102
42
SAIL_RGMII_RESET_SPX8_N
I2S4_WS_MDPX3_1P8
103
43
SAIL_RGMII_INT_SPX8_N
I2S4_DATA0_MDPX3_1P8
104
44
SAIL_RGMII_MDIO_SPX8
I2S4_DATA1_MDPX3_1P8
105
45
SAIL_RGMII_MDC_SPX8
SAIL_CONN_OSPI0_CS0_SPX3_1P8_N
106
46
SAIL_RGMII_RX_CTL_SPX8
SAIL_CONN_OSPI0_DQS_SPX3_1P9
107
47
SAIL_RGMII_RXC_SPX8
SAIL_CONN_OSPI0_WR_SPX3_1P8_N
108
48
SAIL_RGMII_RXD0_SPX8
SAIL_CONN_OSPI0_CLK_SPX3_1P9
109
49
SAIL_RGMII_RXD1_SPX8
SAIL_CONN_OSPI0_DATA_0_SPX3_1P9
110
50
SAIL_RGMII_RXD2_SPX8
SAIL_CONN_OSPI0_DATA_1_SPX3_1P9
111
51
SAIL_RGMII_RXD3_SPX8
SAIL_CONN_OSPI0_DATA_2_SPX3_1P9
112
52
SAIL_RGMII_TX_CTL_SPX8
SAIL_CONN_OSPI0_DATA_3_SPX3_1P9
113
53
SAIL_RGMII_TXC_SPX8
SAIL_CONN_OSPI0_DATA_4_SPX3_1P9
114
54
SAIL_RGMII_TXD0_SPX8
SAIL_CONN_OSPI0_DATA_5_SPX3_1P9
115
55
SAIL_RGMII_TXD1_SPX8
SAIL_CONN_OSPI0_DATA_6_SPX3_1P9
116
56
SAIL_RGMII_TXD2_SPX8
SAIL_CONN_OSPI0_DATA_7_SPX3_1P9
117
57
SAIL_RGMII_TXD3_SPX8
SAIL_RESOUT_SPX3_1P8_N
118
58
GND
MD_GPIO_34_MDPX3_1P8
119
59
VREG_5P0
MD_GPIO_35_MDPX3_1P8
120
60
VREG_5P0
The following table details the pin mapping for the JEXP3 connector.
Table : Pin mapping for the JEXP3 connector
Pin name
Pin number
Pin number
Pin name
MD_GPIO_52_MDPX3_1P8
61
1
EDP2_LN0_P
MD_GPIO_53_MDPX3_1P8
62
2
EDP2_LN0_M
MD_GPIO_54_MDPX3_1P8
63
3
GND
MD_GPIO_55_MDPX3_1P8
64
4
EDP2_LN1_P
MD_RESOUT_MDPX3_1P8_N
65
5
EDP2_LN1_M
PMC_GPIO_7_WLAN_EN_1P8
66
6
GND
HST_SW_CTRL_MDPX3_1P8
67
7
EDP2_LN2_P
PMC_GPIO_8_BT_EN_1P8
68
8
EDP2_LN2_M
BT0_UART_CTS_MDPX3_1P8
69
9
GND
BT0_UART_RFR_MDPX3_1P8
70
10
EDP2_LN3_P
BT0_UART_TX_MDPX3_1P8
71
11
EDP2_LN3_M
BT0_UART_RX_MDPX3_1P8
72
12
GND
MD_GPIO_28_MDPX3_1P8
73
13
EDP2_AUX_P
MD_GPIO_29_MDPX3_1P8
TPM_SPI_PIRQ
74
14
EDP2_AUX_M
BTLE_UART_TX_MDPX3_1P8
75
15
GND
BTLE_UART_RX_MDPX3_1P8
76
16
EDP3_LN0_P
VREG_L8C_UFS1
77
17
EDP3_LN0_M
GND
78
18
GND
DSI1_A0_LN0_P
79
19
EDP3_LN1_P
DSI1_A0_LN0_M
80
20
EDP3_LN1_M
GND
81
21
GND
DSI1_C0_LN1_P
82
22
EDP3_LN2_P
DSI1_A1_LN1_M
83
23
EDP3_LN2_M
GND
84
24
GND
DSI1_B1_CLK_P
85
25
EDP3_LN3_P
DSI1_C1_CLK_M
86
26
EDP3_LN3_M
GND
87
27
GND
DSI1_A2_LN2_P
88
28
EDP3_AUX_P
DSI1_B2_LN2_M
89
29
EDP3_AUX_M
GND
90
30
MDP_VSYNC_MDPX3_1P8
DSI1_C2_LN3_P
91
31
VREG_5P0_PGOOD
DSI1_NC_LN3_M
92
32
PG_VREG_3P3_SIP
GND
93
33
EDP2_HPD_MDPX3_1P8
PMC_GPIO_4_IPA_PWR_EN_1P8
94
34
EDP3_HPD_MDPX3_1P8
PMC_GPIO_5_WLAN_PWR_EN2_1P8
95
35
MD_GPIO_78_MDPX3_1P8
PMC_GPIO_6_WLAN_DBU4_EN_1P8
96
36
DISP_RST_MDPX3_1P8_N
PMC_GPIO_11_WLAN_EN2_1P8
97
37
DISP_INT_MDPX3_1P8_N
PMC_GPIO_12_BT_EN2_1P8
98
38
MD_GPIO_76_MDPX3_1P8
MD_GPIO_79_MDPX3_1P8
99
39
LCD_RESET_MDPX3_1P8
SENSOR_I2C_SDA_MDPX3_1P8
100
40
MD_GPIO_40_MDPX3_1P8
SENSOR_I2C_SCL_MDPX3_1P8
101
41
MD_GPIO_41_MDPX3_1P8
MD_GPIO_84_MDPX3_1P8
102
42
MD_GPIO_42_MDPX3_1P8
MD_GPIO_85_MDPX3_1P8
103
43
MD_GPIO_43_MDPX3_1P8
MD_GPIO_86_MDPX3_1P8
104
44
MD_GPIO_44_MDPX3_1P8
MD_GPIO_87_MDPX3_1P8
105
45
MD_GPIO_45_MDPX3_1P8
MD_GPIO_88_MDPX3_1P8
106
46
PMS_GPIO_4_USB0_VBUS_ON
MD_GPIO_89_MDPX3_1P8
107
47
MD_GPIO_10_MDPX3_1P8
MD_GPIO_90_MDPX3_1P8
108
48
SENSOR_SLP_CLK_MDPX3_1P8
MD_GPIO_140_MDPX3_1P8
109
49
DISP_I2C_SDA_MDPX3_1P8
MD_GPIO_77_MDPX3_1P8
110
50
DISP_I2C_SCL_MDPX3_1P8
MD_DBG_UART_TX_MDPX3_1P8
111
51
MD_GPIO_20_MDPX3_1P8
MD_DBG_UART_RX_MDPX3_1P8
112
52
MD_GPIO_21_MDPX3_1P8
MD_GPIO_56_MDPX3_1P8
113
53
MD_GPIO_22_MDPX3_1P8
MD_GPIO_57_MDPX3_1P8
114
54
MD_GPIO_23_MDPX3_1P8
PMA_GPIO_02_POFF_COMPLETE_3P3_N
115
55
MD_GPIO_36_MDPX3_1P8
PMA_GPIO_06_AOSS_SLP_ENT_3P3
116
56
MD_GPIO_37_MDPX3_1P8
VREG_S5A_WLAN_BT_1P95
117
57
MD_GPIO_38_MDPX3_1P8
VREG_L2C_WLAN_BT_1P05
118
58
IOEXPAN3_INT_MDPX3_1P8_N
VREG_L6E_WLAN_BT_1P35
119
59
MD_GPIO_71_MDPX3_1P8
PMS_GPIO_8_USB1_VBUS_ON
120
60
MD_GPIO_69_MDPX3_1P8
The following table details the pin mapping for the JEXP4 connector.
Table : Pin mapping for the JEXP4 connector
Pin name
Pin number
Pin number
Pin name
SDIO_EMMC_CMD_MDPX7_1P8
61
1
PCIE2USB_PWR_EN_1P8
SDIO_EMMC_CLK_MDPX7_1P8
62
2
PCIE1_MEZZCONN_CLK_N
SDIO_EMMC_RCLK_MDPX7_1P8
63
3
PCIE1_MEZZCONN_CLK_P
SDIO_EMMC_DATA_7_MDPX7_1P8
64
4
GND
SDIO_EMMC_DATA_6_MDPX7_1P8
65
5
PCIE1_MEZZCONN_RX0_N
SDIO_EMMC_DATA_5_MDPX7_1P8
66
6
PCIE1_MEZZCONN_RX0_P
SDIO_EMMC_DATA_4_MDPX7_1P8
67
7
GND
SDIO_EMMC_DATA_3_MDPX7_1P8
68
8
PCIE1_MEZZCONN_RX1_N
SDIO_EMMC_DATA_2_MDPX7_1P8
69
9
PCIE1_MEZZCONN_RX1_P
SDIO_EMMC_DATA_1_MDPX7_1P8
70
10
GND
SDIO_EMMC_DATA_0_MDPX7_1P8
71
11
PCIE1_MEZZCONN_RX2_N
MD_GPIO_68_MDPX3_1P8
72
12
PCIE1_MEZZCONN_RX2_P
PCIE_SWITCH_PWR_EN_1P8
73
13
GND
PCIE2USB_RST_MDPX3_1P8_N
74
14
PCIE1_MEZZCONN_RX3_N
PCIE1_MEZZCONN_RST_1P8_N
75
15
PCIE1_MEZZCONN_RX3_P
PCIE1_MEZZCONN_CLKREQ_1P8_N
76
16
GND
PCIE1_MEZZCONN_WAKE_1P8_N
77
17
PCIE1_MEZZCONN_TX0_N
CAM3_PWR_EN_MDPX3_1P8
78
18
PCIE1_MEZZCONN_TX0_P
PME_GPIO_11_USB2_ID
79
19
GND
CCI6_I2C_SDA_MDPX3_1P8
80
20
PCIE1_MEZZCONN_TX1_N
CCI6_I2C_SCL_MDPX3_1P8
81
21
PCIE1_MEZZCONN_TX1_P
CAM3_MCLK_MDPX3_1P8
82
22
GND
CAM3_PWDN_MDPX3_1P8
83
23
PCIE1_MEZZCONN_TX2_N
CAM3_STROBE_MDPX3_1P8
84
24
PCIE1_MEZZCONN_TX2_P
CAM3_SPARE_GPIO_MDPX3_1P8
85
25
GND
CAM2_PWR_EN_MDPX3_1P8
86
26
PCIE1_MEZZCONN_TX3_N
PME_GPIO_10_USB1_PWR_EN_1P8
87
27
PCIE1_MEZZCONN_TX3_P
CCI4_I2C_SDA_MDPX3_1P8
88
28
GND
CCI4_I2C_SCL_MDPX3_1P8
89
29
CSI3_CONN_NC_CLK_P
CAM2_MCLK_MDPX3_1P8
90
30
CSI3_CONN_A0_CLK_M
CAM2_PWDN_MDPX3_1P8
91
31
CSI3_CONN_B0_LN0_P
CAM2_STROBE_MDPX3_1P8
92
32
CSI3_CONN_C0_LN0_M
CAM2_SPARE_GPIO_MDPX3_1P8
93
33
CSI3_CONN_A1_LN1_P
CAM1_PWR_EN_MDPX3_1P8
94
34
CSI3_CONN_B1_LN1_M
MD_GPIO_12_MDPX3_1P8
95
35
CSI3_CONN_C1_LN2_P
CCI2_I2C_SDA_MDPX3_1P8
96
36
CSI3_CONN_A2_LN2_M
CCI2_I2C_SCL_MDPX3_1P8
97
37
CSI3_CONN_B2_LN3_P
CAM1_MCLK_MDPX3_1P8
98
38
CSI3_CONN_C2_LN3_M
CAM1_PWDN_MDPX3_1P8
99
39
GND
CAM1_STROBE_MDPX3_1P8
100
40
CSI2_CONN_NC_CLK_P
CAM1_SPARE_GPIO_MDPX3_1P8
101
41
CSI2_CONN_A0_CLK_M
CAM0_PWR_EN_MDPX3_1P8
102
42
CSI2_CONN_B0_LN0_P
MD_GPIO_11_MDPX3_1P8
103
43
CSI2_CONN_C0_LN0_M
CCI0_I2C_SDA_MDPX3_1P8
104
44
CSI2_CONN_A1_LN1_P
CCI0_I2C_SCL_MDPX3_1P8
105
45
CSI2_CONN_B1_LN1_M
CAM0_MCLK_MDPX3_1P8
106
46
CSI2_CONN_C1_LN2_P
CAM0_PWDN_MDPX3_1P8
107
47
CSI2_CONN_A2_LN2_M
CAM0_STROBE_MDPX3_1P8
108
48
CSI2_CONN_B2_LN3_P
CAM0_SPARE_GPIO_MDPX3_1P8
109
49
CSI2_CONN_C2_LN3_M
GND
110
50
GND
CSI0_CONN_NC_CLK_P
111
51
CSI1_CONN_NC_CLK_P
CSI0_CONN_A0_CLK_M
112
52
CSI1_CONN_A0_CLK_M
CSI0_CONN_B0_LN0_P
113
53
CSI1_CONN_B0_LN0_P
CSI0_CONN_C0_LN0_M
114
54
CSI1_CONN_C0_LN0_M
CSI0_CONN_A1_LN1_P
115
55
CSI1_CONN_A1_LN1_P
CSI0_CONN_B1_LN1_M
116
56
CSI1_CONN_B1_LN1_M
CSI0_CONN_C1_LN2_P
117
57
CSI1_CONN_C1_LN2_P
CSI0_CONN_A2_LN2_M
118
58
CSI1_CONN_A2_LN2_M
CSI0_CONN_B2_LN3_P
119
59
CSI1_CONN_B2_LN3_P
CSI0_CONN_C2_LN3_M
120
60
CSI1_CONN_C2_LN3_M
Low speed header
In the Dragonwing IQ-9075, there’s one low speed connector (JLS1, 87381-4063) that provides access to various GPIOs, CAN, QUPs, and other interfaces. For the position of this connector, see the Connectors on Dragonwing IQ-9075 EVK.
The following table details the pin mapping for the JLS1 connector
Table : Pin mapping for the JLS1 connector
Pin name
Pin number
Pin number
Pin name
GND
1
2
GND
MD_GPIO_52_3P3 (UART CTS)
3
4
CAN_H
MD_GPIO_54_3P3 (UART TX)
5
6
CAN_L
MD_GPIO_55_3P3 (UART RX)
7
8
MD_GPIO_32_3P3 (SPI MISO)
MD_GPIO_53_3P3 (UART RFR)
9
10
MD_GPIO_33_3P3 (SPI MOSI)
MD_GPIO_44_3P3 (UART TX)
11
12
MD_GPIO_34_3P3 (SPI CLK)
MD_GPIO_45_3P3 (UART RX)
13
14
MD_GPIO_35_3P3 (SPI CS)
EXP_I2C_SCL_3P3 (GPIO 95)
15
16
SOC_MI2S1_WS_3P3
EXP_I2C_SDA_3P3 (GPIO 96)
17
18
SOC_MI2S1_SCK_3P3
SENSOR_I2C_SCL_3P3
19
20
SOC_MI2S1_DATA1_3P3
SENSOR_I2C_SDA_3P3
21
22
SOC_MI2S1_DATA0_3P3
MD_GPIO_40_3P3 (UART CTS)
23
24
SOC_MI2S_MCLK0_3P3
MD_GPIO_41_3P3 (UART RFR)
25
26
MD_GPIO_43_3P3 (UART RX)
MD_GPIO_42_3P3 (UART TX)
27
28
SAIL_GP1_CLK_A_3P3
PME_GPIO_11_USB2_ID
29
30
SAIL_GP3_CLK_A_3P3
MD_GPIO_140_3P3
31
32
SAIL_GP4_CLK_A_3P3
IOEXPAN3_GPIO_7_3P3
33
34
SAIL_GP5_CLK_A_3P3
VREG_3P3_SIP
35
36
VREG_SYSTEM_PWR
VREG_5P0
37
38
VREG_SYSTEM_PWR
GND
39
40
GND
Debug interface
The platform includes a micro-USB connector receptacle (JTAC, part number: 0475890001) connected to an FTDI chip (U19, part number: FT4232HL-REEL), which is used for debugging purposes.
For the location of the debug interface connector on the platform, see the Connectors on Dragonwing IQ-9075 EVK.
JTAG interface
The JTAG connector header on the board is a 20-position pin interconnect with a 0.050” (1.27 mm) pitch and 0.050” (1.27 mm) row spacing. The reference designator for the JTAG connector component is JTAG, and its part number is FTSH-110-01-L-D-RA-K. To use a traditional JTAG connector, an adapter such as the 65-PM339-1 may be required.
For the location of the JTAG connectors on the platform, see the Connectors on Dragonwing IQ-9075 EVK.
Audio
For speaker and audio support, the HS0_MI2S interface is used for the two onboard audio amplifiers, and the HS2_MI2S interface is used for the I2S microphone on the mainboard. Both interfaces can optionally be switched to the mezzanine connectors for expansion purposes.
Consider the following details about speakers and microphones on the device:
Speakers: Onboard speakers (with MAX98357 I2S-amps); HS0_MI2S is shared between both left and right speakers to enable stereo sound.
Microphones: The EVK includes a single onboard microphone (MMICT5848) that uses the HS2_MI2S interface. By default, the microphone is configured to the left channel. To switch the microphone to the right channel, rework or move resistor R180 to R179 location. For more information about the location of resistor, see the Design Package, IQ-9075 EVK Design Files (DP25-73418-42).
The following figure shows the audio interfaces and configuration.
Third-party
Connectors
Primary interfacesignals
Control / Power/ Auxiliary signals
Qualcomm
IQ-9075M SoC
U7
JEXP2
JSPKR
MEMSmicrophone
120-pinB2B expansionconnector
Surfacemount 4-pin connector
GPIO_114/115/116/117
GPIO_95/96
S10
U34
U35
GM1
AB switch
U69
GPIO Expander
SEL
I2Caddr:0x39
P4
Dx
SxA
SxB
HS0_MI2S
HS0_MI2S_CONN
SPK_SEL
GPIO_118/119/120/121
S11
AB switch
SEL
Dx
SxA
SxB
HS1_MI2S
HS1_MI2S
SPK_SEL
GPIO_122/123/124/125
S12
AB switch
SEL
Dx
SxA
SxB
HS2_MI2S
HS2_MI2S
HS2_MI2S
SEL
SPKR_OUT_L
SPKR_OUT_R
Audioamplifier
HS1_MI2S
Audioamplifier
HS0_MI2S
U68
I2C_SDA/SCL
I2C_SDA/SCL
GPIO Expander
I2Caddr:0x38
P7
Figure : Audio interfaces and configuration
The following figure shows the Dragonwing IQ-9075 EVK connected to two mini speakers.
../../_images/speakers-connected.png
Figure : Dragonwing IQ-9075 EVK connected to two mini speakers
Thermal management and fan control
The Dragonwing IQ-9075 EVK is designed to consume up to 70 W, necessitating a substantial thermal solution. The default cooling solution is fan-based, which uses a CPU cooler mounted to the bottom of the device.
The following figures show the thermal management solutions implemented in the Dragonwing IQ-9075 EVK. The fan controller used on this board is a Texas Instruments AMC6821SQDBQRQ1 PWM fan controller IC. The fan used in the system is connected using JFAN connector (S6B-XH-SM4-TB(LF)(SN)) on the mainboard.
Future versions of the device may offer different thermal options, including smaller fans or heatsinks, depending on the expected use cases.
../../_images/thermal-management-on-iq9075-evk.png
Figure : Thermal management on Dragonwing IQ-9075 EVK
Accessory boards
This information will be provided in a future revision of the document.
Next steps
Set up the device.
Run sample applications.
Develop an application.