> ## Documentation Index
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> Use this file to discover all available pages before exploring further.

# Hardware overview

The Qualcomm DragonwingTM IQ-9075 Evaluation Kit (EVK) has the IQ-9075M module. Learn more about the system block diagram, electrical design, features, and capabilities of the EVK.

System block diagram

The following figure shows the system block diagram of the Dragonwing IQ-9075 EVK platform. This figure provides a visual representation of the platform’s architecture, highlighting the main components and their interactions.

../../\_images/1-5-iq9-system-block-diagram-03.png

Figure : Dragonwing IQ-9075 EVK system block diagram

Hardware specification

The following table outlines the key hardware specification of the Dragonwing IQ-9075 EVK.

Note

For the list of interfaces supported in this release, see the Qualcomm Linux 2.0 Release Notes.

Table : Dragonwing IQ-9075 EVK key specifications

Interface or feature

Description

SoC

IQ-9075 (part of IQ-9075M)

Memory

6 × 16 bit 36 GB LP5 3200 MHz (3x 12GB LPDDR5) (part of IQ-9075M)

PMIC

4 × PMM8650AU (part of IQ-9075M)

External MCU

Not present

Storage

2 × 128 GB UFS, micro-SD card, EEPROMs for MACs, eMMC on mezzanine card

Display

Four display ports:

2 × mini-DP (one with MST)

2 × DSIs (one to DSI flex, one to expansion)

DSI flex connection with touchscreen

Camera/Video input

4 × Quad deserializers

4 × CSI (C-PHY or D-PHY) cameras

USB

USB0 Type-C (host or device mode)

USB1 Type-C (host mode)

USB2 uUSB 2.0 (host or device mode)

WLAN/Bluetooth®

m.2 module (NFA765A)

2 × printed antennas (Bluetooth shared with one WLAN antenna)

PCIe

Mainboard supported or expanded options (selected through switch):

1 × PCIe x4 slot or expansion (switch)

1 × m.2 E key (WI-Fi) or expansion (switch)

Audio

1 × I2 S mic

2 × I2 S speaker amps

Additional I2 S on GPIOs

Ethernet

RJ45 2.5 GbE MD

CAN/CAN-FD

1 × CAN/CAN-FD on low speed header on mainboard

Low-speed expansion

3.3 V header for developer community with CAN, SPI, I2 C, UART, I2 S

Second low-speed expansion

QUPs and GPIOs on mezzanine connectors

Sensors

IMU: ICM-42688

QUPs on expansion

Trusted platform module (TPM)

ST33HTPH2x32AHE4 on mainboard

Exterior view

The following figures show the exterior of the Dragonwing IQ-9075 EVK with the bottom case.

../../\_images/1-5-exterior-evk-top-view-and-with-casing.png

Figure : Exterior view of the EVK with bottom case

The following figures show the side views of the Dragonwing IQ-9075 EVK, with labeled ports, connectors, and switches.

../../\_images/iq9-views.png

The following figure shows the top view of the core board.

../../\_images/1-5-1-iq9-top-view\.png

Figure : Top view of the core board

EVK ports and interfaces

The following figure shows a detailed view of all the connectors on the Dragonwing IQ-9075 EVK.

../../\_images/1-5-iq9-top-view\.png

Figure : Connectors on Dragonwing IQ-9075 EVK

The following figure shows the platform with few cables plugged in.

../../\_images/1-5-iq9-with-cables.png

Figure : Platform with cables plugged in

Table : Connectors and functions

Connectors

Functions

JPWR

DC power (barrel connector) plug, 12 V–36 V input voltage

JLS1

Low speed IO header receptacle (LS1)

SW1

8 position surface mount DIP switch

SW2

4 position surface mount DIP switch

SW3

6 position surface mount DIP switch

JCAM0

MIPI CSI0 camera interconnect receptacle

JCAM1

MIPI CSI1 camera interconnect receptacle

JCAM2

MIPI CSI2 camera interconnect receptacle

JCAM3

MIPI CSI3 camera interconnect receptacle

JPCIE

PCI Express v4 receptacle connector (PCIe1)

JEDP1

EDP1 connector

JEDP0

EDP0 connector

JETH

Ethernet connector (2.5 GbE)

JUSB1

USB-C (USB Type-C) receptacle connector for USB1

JUSB0

USB-C (USB Type-C) receptacle connector for USB0

JUSB2

Micro-USB receptacle for USB2

JRST

Tactile switch for system reset (initiates graceful shutdown)

J13

Antenna for WLAN

S4

Slide switch for power or automation control

JDISP

Connector for DSI display

JTAC

Micro-USB receptacle for debug UART

JTAG

Header connector for JTAG

J14

Antenna for WLAN/Bluetooth

JEXP1–JEXP4

Board-to-board 120 position connector receptacle

DIP switch

The following images show the location of the DIP switches on the mainboard.

../../\_images/1-5-iq9-dip-switches-2.png

Figure : DIP switches 1, 2, and 3 on Dragonwing IQ-9075 EVK

../../\_images/1-5-1-dip-switches-4-7-8-9.png

Figure : DIP switches 4, 7, 8, and 9 on Dragonwing IQ-9075 EVK

Note

If a DIP switch is facing up, it indicates that the switch is on.

The following table details DIP switch operations for the Dragonwing IQ-9075 EVK, including functions and settings for board configuration.

Table : DIP switch position and its respective functions

Switch

Connection when ON

Connection when OFF (default from factory)

Notes

SW1-1

PCIe0 is routed to mezzanine

PCIe0 is connected to the mainboard Wi-Fi module

SW1-2

PCIe1 is routed to mezzanine

PCIe1 is connected to the mainboard PCIe connector

SW1-3

SDIO is routed to mezzanine

SDIO is routed to the mainboard SD card

SW1-4

DSI is routed to mainboard flex connector

DSI is routed to mezzanine

SW1-5

CSI0 is routed to mezzanine

CSI0 is routed to the mainboard CSI flex connector

SW1-6

CSI1 is routed to mezzanine

CSI1 is routed to the mainboard CSI flex connector

SW1-7

CSI1 is routed to mezzanine

CSI2 is routed to the mainboard CSI flex connector

SW1-8

CSI2 is routed to mezzanine

CSI3 is routed to the mainboard CSI flex connector

SW2-1

Main domain forced USB boot/EDL

No impact

Currently, this switch isn’t enabled in software.

SW2-2

Main domain fast boot

No impact

SW2-3

Main domain and Sail domain forced USB boot/EDL (combined)

No impact

Currently, the software implementation puts both domains into EDL mode together. It’s important for software download.

SW2-4

Sail domain Fastboot mode

No impact

SW3-1

OSPI is routed to mezzanine

OSPI is connected to onboard memory for MCU

SW3-2

Force MD and MCU PS\_HOLD

No impact

SW3-3

Watchdog is disabled

RAM dump is enabled

SW3-4

Boot from eMMC

Boot from UFS

eMMC located on interface and mezzanine

SW3-5

EUD enable

No impact

SW3-6

Skip MD BIST

No impact

SW4-1

Reserved for internal use

Don’t change.

SW7-1

Reserved for internal use

Don’t change.

SW8-1

Reserved for internal use

Don’t change.

SW9-1

Reserved for internal use

Don’t change.

LEDs

The Dragonwing IQ-9075 EVK has status LEDs that monitor system functions such as power-on and board faults, crucial for debugging and bringup. The following table lists and summarizes the functions of the LEDs. The Connectors on Dragonwing IQ-9075 EVK shows the location and the LEDs present on the board.

Table : Summary of reference designator, location, color, and function of LEDs

Reference designator

Location

Color

Function

DS1

Mainboard

Green

Reserved for debugging

DS8

Mainboard

Green

Ethernet status LEDs

DS9

Mainboard

Green

DS10

Mainboard

Green

VREG\_3P3\_SIP indicator

DS11

Mainboard

Orange

VREG\_3P3\_SIP indicator

LED1

Mainboard

RGB

Software-controlled RGB lighting through GPIOs

Hardware components and interfaces

Review the following high-level details of Dragonwing IQ-9075 processor, power supply, memory, and various interfaces, such as camera, USB, and DisplayPort. It also includes sensors, flash memory, expansion options, a debug interface, audio support, thermal management, fan control, and accessory boards.

Processor

The target processor used in the Dragonwing IQ-9075 EVK is the Dragonwing IQ-9075 SoC, also known as the IQ-9075. This SoC features an octa-core Kryo™ Gen 6 CPU built on Arm v8.2 Cortex technology, with clock support up to 2.55 GHz.

In addition to the eight high-performance CPU cores, the SoC includes a GPU and two Hexagon Tensor Processors with vector and matrix extensions, enabling the management of various concurrent compute and AI workloads simultaneously. The SoC offers extensive peripheral support, including integrated Ethernet, USB, Wi-Fi, PCIe, and Bluetooth. It’s capable of delivering up to 100 INT8 TOPS, making it suitable for powering high-performance, AI-centric, and Edge AI industrial use cases.

The target applications include:

Factory automation

Industrial robots

Industrial personal computers

Drones

Edge AI Boxes

Machine Vision

Autonomous Mobile Robots (AMRs)

Industrial gateways

The IQ-9075 SoC is integrated within the IQ-9075M module, which also houses the four PMICs and three LPDDR5 SD RAM memory components. The following figure shows the IQ-9075 SoC within IQ-9075M module.

../../\_images/1-5-1-iq9-soc-module.png

Figure : IQ-9075 SoC within IQ-9075M module

Power

The main power input to the Dragonwing IQ-9075 board is provided through the 2.10 mm barrel jack connector (JPWR, JACK-C-PC-10A-RA(R)), supporting an input voltage range of 12 V to 36 V. The EVK also includes a Type-C to barrel plug adapter. Four power management ICs manage the respective power supplies to various system blocks, including the SoC, PMIC, PCIe, and expansion ports.

The following figure shows the four PMICs on the IQ-9075M module.

../../\_images/1-5-1-iq9-pmic.png

Figure : Four PMICs on the IQ-9075M module

Memory

The IQ-9075M module has three 12 GB LPDDR5 SDRAM ICs. The following figure shows the LPDDR5 memory ICs on the module.

../../\_images/1-5-1-iq9-memory.png

Figure : LPDDR5 memory on the IQ-9075M module

Camera interface

An analog switch is used for each MIPI CSI interface, allowing the MIPI CSI interfaces to be accessible through both the JCAM camera interconnect receptacle and the B2B expansion connector (JEXP4).

For more information about camera mezzanine board, see the Qualcomm Dragonwing IQ-9075 PVT GMSL Mezzanine Interface User Guide.

The following table lists the CSI interfaces, their analog switch, camera connector, and B2B connector pinout.

Note

You can connect the CSI interfaces to the mainboard connector or to GMSL mezzanine through a DIP switch setting. For the correct setting, see the Table: DIP switch position and its respective functions.

Table : CSI settings

CSI interface

Analog switch

Camera connector

B2B connector pinout

CSI0

U45

(TMUX646ZECR)

JCAM0

JEXP4, Pins 111-120

CSI1

U42

(TMUX646ZECR)

JCAM1

JEXP4, Pins 51-60

CSI2

U44

(TMUX646ZECR)

JCAM2

JEXP4, Pins 40-49

CSI3

U43

(TMUX646ZECR)

JCAM3

JEXP4, Pins 29-38

The four MIPI CSI ports can operate in either C-PHY or D-PHY mode. They support a range of existing cameras and flexes, including the OV9282 and IMX577.

To use a GMSL camera with the Dragonwing IQ-9075 EVK, connect it through the GMSL mezzanine, which must be ordered separately. The CSI ports are routed through the DIP switches, allowing configuration and setup.

Note

Four cameras have been validated concurrently, which includes two YUV GMSL cameras connected to GMSL Port2 and Port3, and two MIPI camera connected to MIPI CSI0 and CSI1 slots.

The following figure shows the Dragonwing IQ-9075 EVK with different camera configurations.

../../\_images/evk-with-gmsl-mezzanine-attached-csi-camera-rpi-adapter.png

Figure : Dragonwing IQ-9075 EVK with (L) GMSL mezzanine attached; (R) MIPI CSI cameras

The following figure shows the camera interfaces and configuration.

IQ-9075M SoC

U7

SW1

DIPswitch

JEXP4

JCAM0

CSI0 CLK/LNx

GPIO\_60

CCI0\_I2C\_SDA\_MDPX3\_1P8

CCI0\_I2C\_SCL\_MDPX3\_1P8

CAM0\_MCLK\_MDPX3\_1P8

GPIO\_61

GPIO\_72

U45

AB switch

SEL

Dx

SxA

SxB

CSI0 CLK/LNx

CSI0 CLK/LNx

CSI0 CLK/LNx

CAM0\_DIP\_SW

JEXP4

JCAM1

CSI1 CLK/LNx

GPIO\_62

CCI2\_I2C\_SDA\_MDPX3\_1P8

CCI2\_I2C\_SCL\_MDPX3\_1P8

CAM1\_MCLK\_MDPX3\_1P8

GPIO\_63

GPIO\_73

U42

AB switch

SEL

Dx

SxA

SxB

CSI1 Data

CSI1 CLK/LNx

CSI1 CLK/LNx

CAM1\_DIP\_SW

JEXP4

JCAM2

CSI2 CLK/LNx

GPIO\_64

CCI4\_I2C\_SDA\_MDPX3\_1P8

CCI4\_I2C\_SCL\_MDPX3\_1P8

CAM2\_MCLK\_MDPX3\_1P8

GPIO\_65

GPIO\_74

U44

AB switch

SEL

Dx

SxA

SxB

CSI2 Data

CSI2 CLK/LNx

CSI2 CLK/LNx

CAM2\_DIP\_SW

JEXP4

JCAM3

CSI3 signals

GPIO\_66

CCI6\_I2C\_SDA\_MDPX3\_1P8

CCI6\_I2C\_SCL\_MDPX3\_1P8

CAM2\_MCLK\_MDPX3\_1P8

GPIO\_67

GPIO\_75

U43

AB switch

SEL

Dx

SxA

SxB

CSI3 Data

CSI3 CLK/LNx

CSI3 CLK/LNx

CAM3\_DIP\_SW

Third-party

Connectors

Primary interfacesignals

Control / Power/ Auxiliary signals

Qualcomm

Figure : Camera interfaces and configuration

USB interface

The board features three USB connectors: two Type-C connectors (USB0 and USB1) and one micro-USB connector (USB2). The following table outlines the USB properties of the board. Connectors on Dragonwing IQ-9075 EVK shows the location of the USB connectors on the board.

Table : Reference designator, USB interface and type

Reference designator

USB interface and type

Description

JUSB0

USB0 USB-C (USB Type-C)

USB 3.1 Gen 2, HS + SS, supports host or device mode

JUSB1

USB1 USB-C (USB Type-C)

USB 3.1 Gen 2, HS + SS, supports host mode

JUSB2

USB2 Micro-USB

USB2.0, HS, supports host modes

The following figure shows the USB interfaces and configuration.

IQ-9075M SoC

U7L

JUSB0

USB Type Cconnector(USB0)

JUSB1

USB Type Cconnector(USB1)

JUSB2

Micro USBconnector(USB2)

USB0 SS

USB0 HS

PME\_GPIO\_4

GPIO\_50

GPIO\_48/49

PME\_GPIO\_5

U91

Port controller

USB\_VBUS

I2C addr: 0x67

Port controller

USB\_VBUS

I2C addr: 0x47

U110

U111

U92

U69

(blue wire)

I2C\_SDA/SCL

Voltage divider

Voltage divider

EN

(blue wire)

EN

5V supply(for host mode)

5V supply(for host mode)

U6

5 V supply(for host mode)

GPIO expander

GPIO\_95/96

GPIO\_19

GPIO\_81

GPIO\_80

USB1 HS/SS

PME\_GPIO\_6

GPIO\_51

VREG\_5P0

ID driven low if downstreamdevice connected

VREG\_3P3\_SIP

VREG\_MDPX3\_1P8

USB0 SS

USB1 HS/SS

USB SS

USB0 HS

USB HS

USB2\_ID

USB2 HS

USB0 SS

USB0\_ID

I2C\_SDA/SCL

INT\_N

VREG\_5P0

VREG\_3P3\_SIP

VREG\_MDPX3\_1P8

FAULT\_N

No connect

FAULT\_N

No connect

INT\_N

FAULT\_N

USB0\_VBUS

From connector(device mode)or into connector(host mode)

USB1\_ID

I2C\_SDA/SCL

I2C\_SDA/SCL

PMC\_GPIO\_10

PMC\_GPIO\_9

PME\_GPIO\_11

USB2 HS

FAULT\_N

EN

INT\_N

CC1/CC2

USB SS

CC1/CC2

USB2\_VBUS

From connector(device mode)or into connector(host mode)

USB1\_VBUS

Into connector(host mode only)

Third-party

Connectors

Primary interfacesignals

Control / Power/ Auxiliary signals

Qualcomm

ID driven low if downstreamdevice connected

I2Caddr:0x39

U103

GPIO expander

I2Caddr:0x3b

P2

P3

P3

P5

U40

USB hub

USB\_VBUS\_DET

USB\_RESET\_N

I2C

I2C addr: 0x25

USB interfaces and configuration

DisplayPort (eDP) interface

The target processor is equipped with four eDP interfaces. EDP0 and EDP1 are routed to the DP connector receptacles JEDP0 and JEDP1, respectively.

For the location of the DP connectors on the platform, see the Connectors on Dragonwing IQ-9075 EVK.

Table : eDP interface connections

eDP interface

Connected to

EDP0

JEDP0 (DP3AR020SU32JQ1R400)

EDP1

JEDP1 (DP3AR020SU32JQ1R400)

The following figure shows the eDP interfaces and configuration.

IQ-9075M SoC

U7

DP connector3VT11207-N730-7H(ESD protected)

JEDP0

DP connector3VT11207-N730-7H(ESD protected)

JEDP1

120-pin B2Bexpansionconnector

JEXP3

EDP0 AUX/LNx

GPIO\_101

EDP0 AUX/LNx

EDP0\_HPD\_MDPX3\_1P8

EDP1 AUX/LNx

GPIO\_102

EDP2 AUX/LNx

EDP3 AUX/LNx

GPIO\_103

GPIO\_104

EDP1 AUX/LNx

EDP1\_HPD\_MDPX3\_1P8

EDP2 AUX/LNx

EDP3 AUX/LNx

EDP2\_HPD\_MDPX3\_1P8

EDP3\_HPD\_MDPX3\_1P8

Connectors

Primary interfacesignals

Control / Power/ Auxiliary signals

Qualcomm

eDP interfaces and configuration

DSI interface

The IQ-9075 processor supports two 4-lane MIPI-DSI with VESA DSC v1.2.

The Dragonwing IQ-9075 EVK uses an analog switch for DSI0 interface, allowing the interface to be accessible through both the JDISP LCD receptacle and the B2B expansion connector (JEXP1).

Note

Due to the analog switch, you can connect the DSI0 interfaces to the mainboard LCD connector or to the GMSL mezzanine through a DIP switch setting. For the intended DSI setting, see the Table: DIP switch position and its respective functions.

The software support for DSI interface will be provided in a future release.

The following figure shows DSI interfaces and configuration.

IQ-9075M SoC

U7

SW1

DIPswitch

120-pin B2Bexpansionconnector

JEXP3

Displayconnector

JDISP

JEXP3

DSI0 CLK/LNx

GPIO\_24

DISP\_I2C\_SDA\_MDPX3\_1P8

DISP\_I2C\_SCL\_MDPX3\_1P8

TOUCH\_INT\_MDPX3\_1P8\_N

GPIO\_25

GPIO\_72

U46

AB switch

SEL

Dx

SxA

SxB

DSI0 CLK/LNx

DSI0 CLK/LNx

DSI0 CLK/LNx

DSI0\_DIP\_SW

120-pin B2Bexpansionconnector

DSI1 CLK/LNx

DSI1 CLK/LNx

DSI0-1 routed differentially in D-PHY mode

Third-party

Connectors

Primary interfacesignals

Control / Power/ Auxiliary signals

Qualcomm

Figure : DSI interfaces and configuration

Storage interfaces

The Dragonwing IQ-9075 device has three types of storage interfaces: secure digital (SD) card, universal flash storage (UFS), and electrically erasable programmable read-only memory (EEPROM).

SD card

The target processor supports a single SDIO interface (SDC1). The SDC pins are routed through analog switches (U2, U3) to facilitate connections through the micro SD card connector (JSDC) on the board, and through the expansion connector (JEXP4, pins 61–71) for eMMC connectivity on a mezzanine board.

Note

You can connect the SDIO to the mezzanine or the micro SD card through a DIP switch setting. For the correct setting, see the Table: DIP switch position and its respective functions.

The following table lists the SDC interfaces on the board.

Table: SDC interfaces

SDC interface

Analog switch

uSD connector

B2B connector pinout

SDC1

U2, U3 (PI3A27518ZDEX\_QFN24P)

JSDC

JEXP4, pins 61-71

The following figure shows the SD card interfaces and configuration.

IQ-9075M SoC

U7K

SW1

JSDC

SW1

JEXP4

DIPswitch

120-pin B2Bexpansionconnector

MICRO SD cardconnector(ESD protected)

GPIO\_36

SDC1 CLK/CMD/DATA\[0:3]

SDC1 RCLK/DATA\[4:7]

SDC CLK/CMD/DATA\[0:4]

U2

U119

6-channel, 1:2multiplexer/demultiplexer

Voltage level translatorwith EMI filter andESD protection

IN1

COMx

NCx

NOx

SDC RCLK/DATA\[4:7]

U3

6-channel, 1:2multiplexer/demultiplexer

IN1

COMx

NCx

NOx

SDC CLK/CMD/DATA\[0:4]

SDC CLK/CMD/DATA\[0:4]

SDC CLK/CMD/DATA\[0:4]

SDC RCLK/DATA\[4:7]

SDIO\_MUX\_SEL

SDIO\_MUX\_SEL

SDCARD\_DET\_MDPX3\_1P8\_N

Third-party

Connectors

Primary interfacesignals

Control / Power/ Auxiliary signals

Qualcomm

SD card interfaces and configuration

Note

Additional components on eMMC signals may negatively impact signal integrity, potentially leading to boot failures. The existing circuitry isn’t optimal and shouldn’t be replicated. For the best performance and higher speed support, a cleaner layout is recommended.

UFS

The target processor supports two UFS 3.1 Gear 4 interfaces, each with two lanes for on-board memory. UFS0 serves as the main domain boot-up device. The Dragonwing IQ-9075 EVK platform is equipped with two 128 GB UFS devices on the mainboard.

The following table lists the part numbers and manufacturers of these UFS devices.

Table : Part numbers and manufacturers of UFS devices

Reference designator

Interface identifier

MPN

Manufacturer

Description

U38

UFS0

THGJFGT0T25BAB8

KIOXIA AMERICA INC

128 GB UFS3.1 (Gear4) Q100-GR2 RoHS

U39

UFS1

The following figure shows the UFS interfaces and configuration.

IQ-9075M SoC

U7K

U38

Switches

UFS0 REFCLK/RESET/DATA

UFS0 REFCLK/RESET/DATA

Flash memory128 GB

THGJFGT0T25BAB8

U39

UFS1\_VCC

UFS1\_VCCQ

UFS1\_VCCQ2

UFS1 REFCLK/RESET/DATA

UFS1 REFCLK/RESET/DATA

Flash memory128 GB

THGJFGT0T25BAB8

UFS0\_VCC

UFS0\_VCCQ

UFS0\_VCCQ2

Primary interfacesignals

Control / Power/ Auxiliary signals

Third-party

Qualcomm

UFS interfaces and configuration

EEPROM

The Dragonwing IQ-9075 EVK platform has a single EEPROM device dedicated to storing MAC addresses for Ethernet, Wi-Fi, and Bluetooth.

The following table lists the part number and manufacturer of the EEPROM device.

Table : Part number and manufacturer of the EEPROM device

Reference designator

Device

MPN

Manufacturer

Description

U20

EEPROM

93LC46B-I/SN

Microchip Technology Inc.

1 Kbit low-voltage serial electrically erasable PROMs (EEPROM)

On-board sensors

The Dragonwing IQ-9075 EVK platform includes an on-board IMU and a temperature sensor. They are connected to the real-time subsystem (RTSS) domain of IQ-9075 EVK.

Note

Currently, the software doesn’t support the IMU and temperature sensors.

The following table lists the part numbers and manufacturers of these sensors.

Table : Part numbers and manufacturers of the sensors

Reference designator

Sensor type

Communication protocol used

MPN

Manufacturer

U97

IMU sensor

I2C

ICM-42688

TDK InvenSense

U109

Temperature sensor

SPI

TMP411DQDGKRQ1

Texas Instruments

PCIe interface

The target processor supports two PCIe interfaces: PCIe0 and PCIe1. PCIe0 is Gen4 2-lane and PCIe1 is Gen4 4-lane PCIe interface.

Both PCIe interfaces are connected to an A/B switch, which by default, connects them to the expansion mezzanine. Configure the DIP switches to connect the PCIe0 to the Wi-Fi/Bluetooth module and PCIe1 to the full size PCIe x4 connector on the mainboard. For DIP switch settings, see the Table: DIP switch position and its respective functions.

For more information about the mezzanine board, see the Qualcomm Dragonwing IQ-9075 PVT IFP Mezzanine Board User Guide.

The following figure shows the PCIe interfaces and configuration.

IQ-9075M SoC

U7

SW1

JBTWL

JPCIE

S6, U15, U16, U17

DIPswitch

PCIe x4connector

120-pin B2Bexpansionconnector

JEXP4

JEXP1

M.2 connectorfor Wi-Fi/BTmodule

Switches

S6: GPIO\_3 to GPIO\_5U15, U16, U17: REFCLK, TX, RX

PCIE0 CLK/TX/RX

GPIO\_0

PCIE0\_WAKE

PCIE0\_CLKREQ

PCIE0\_RST

GPIO\_1

GPIO\_2

S5, U10, U11, U12

Switches

S5: GPIO\_0 to GPIO\_2U10, U11, U12: REFCLK, TX, RX

SEL

PCIE0 CLK/TX/RX

PCIE0 CLK/TX/RX

PCIE0 GPIOs

PCIE0 CLK/TX/RX

PCIE0 GPIOs

PCIE1 CLK/TX/RX

PCIE1 GPIOs

PCIE1 CLK/TX/RX

PCIE1 GPIOs

PCIE1 CLK/TX/RX

GPIO\_3

PCIE1\_CLKREQ

PCIE1\_RST

PCIE1\_WAKE

GPIO\_4

GPIO\_5

SEL

PCIE1 CLK/TX/RX

PCIE1\_MUX\_SEL

PCIE0\_MUX\_SEL

120-pin B2Bexpansionconnector

Third-party

Connectors

Primary interfacesignals

Control / Power/ Auxiliary signals

Qualcomm

Figure : PCIe interfaces and configuration

Flash memory

The Dragonwing IQ-9075 EVK uses OSPI interface to support 2GBIT flash memory. The analog switch for OSPI interface allows the interface to be accessible through both the flash memory device and the B2B expansion connector (JEXP2).

Note

Due to the analog switch, you can connect the OSPI to the memory device or to B2B connector through DIP switch settings. For the intended OSPI settings, see the Table: DIP switch position and its respective functions.

The following figure shows the flash memory interfaces and configuration.

IQ-9075M SoC

U7

SW3

U41

DIPswitch

NOR flash memory

120-pin B2Bexpansionconnector

JEXP2

SAIL\_IO\_71 to 78

SAIL\_IO\_67

OSPI0\_CS0

OSPI0\_DQS

OSPI0\_WR

Test point(TP35)

SAIL\_IO\_68

SAIL\_IO\_68

S7, S8, S9

A/B switches

SEL

Dx

SxA

SIOx

SxB

OSPI0\_DATA\[0:7]

OSPI0\_DATA\[0:7]

VREG\_SPX3\_1P8

Flash GPIOs

OSPI0\_DATA\[0:7]

Flash GPIOs

OSPI\_MUX\_SEL

Third-party

Connectors

Primary interfacesignals

Control / Power/ Auxiliary signals

Qualcomm

Figure : Flash memory interfaces and configuration

The following figures show controller area network (CAN) block diagram and interfaces.

IQ-9075M SoC

Voltage leveltranslator(TXB0108NMER)

CAN device

CAN

RTSS\_IO\_38

RTSS\_IO\_37

QUP SE4with SPI

B3

B2

B1

B4

RTSS\_IO\_5

A4

RTSS\_IO\_4

A3

RTSS\_IO\_2

A2

RTSS\_IO\_3

TLE9255WLC

A1

VCCB

VCCA

CSN

SCLK

MISO

MOSI

RXD

VCC

5 V

3.3 V

1.8 V

12 V

3.3 V

VBAT

VIO

TXD

CANL

CANH

CANL

CANH

WAKE

Qualcomm

Figure : CAN0 interfaces

IQ-9075M SoC

CAN device

CAN

RTSS\_CAN\_RX

RTSS\_CAN\_TX

ADM3058EBRIZ-RL

RXD

VDD1

1.8 V

5 V

VDD2

TXD

CANL

CANH

CANL

60.4 kΩ

4.7 nF

60.4 kΩ

CANH

Qualcomm

Figure : CAN1 to CAN7 interfaces

Expansion headers

The Dragonwing IQ-9075 EVK features four high-speed expansion connectors (JEXP1-4, 10139781-121422LF). Connect accessory cards such as GMSL mezzanine and RBx adapters to these connectors. Additionally, other interfaces mentioned throughout this document are also routed to these connectors. For the position of the connectors, see the Connectors on Dragonwing IQ-9075 EVK.

For more information about the mezzanine board, see the Qualcomm Dragonwing IQ-9075 PVT IFP Mezzanine Board User Guide.

The following table details the pin mapping for the JEXP1 connector.

Table : Pin mapping for the JEXP1 connector

Pin name

Pin number

Pin number

Pin name

GND

61

1

VREG\_SYSTEM\_PWR

DSI0\_A0\_LN0\_P\_CONN

62

2

VREG\_SYSTEM\_PWR

DSI0\_B0\_LN0\_M\_CONN

63

3

VREG\_SYSTEM\_PWR

GND

64

4

VREG\_SYSTEM\_PWR

DSI0\_C0\_LN1\_P\_CONN

65

5

VREG\_SYSTEM\_PWR

DSI0\_A1\_LN1\_M\_CONN

66

6

GND

GND

67

7

GND

DSI0\_B1\_CLK\_P\_CONN

68

8

GND

DSI0\_C1\_CLK\_M\_CONN

69

9

GND

GND

70

10

VREG\_3P3\_SIP

DSI0\_A2\_LN2\_P\_CONN

71

11

VREG\_3P3\_SIP

DSI0\_B2\_LN2\_M\_CONN

72

12

GND

GND

73

13

GND

DSI0\_C2\_LN3\_P\_CONN

74

14

PME\_GPIO\_3\_USB1\_FAULT\_3P3\_N

DSI0\_NC\_LN3\_M\_CONN

75

15

PME\_GPIO\_4\_USB0\_FAULT\_3P3\_N

GND

76

16

MD\_GPIO\_17\_MDPX3\_1P8

VREG\_L7C\_1P8

77

17

MD\_GPIO\_18\_MDPX3\_1P8

GND

78

18

SGMII0\_MDC\_MDPX3\_1P8

VREG\_MDPX3\_1P8

79

19

SGMII0\_MDIO\_MDPX3\_1P8

GND

80

20

SGMII0\_CONN\_RX\_P

IOEXPAN1\_INT\_MDPX3\_1P8\_N

81

21

SGMII0\_CONN\_RX\_M

STR\_WAKE\_MDPX3\_1P8

82

22

SGMII0\_CONN\_TX\_P

SGMII1\_RX\_P

83

23

SGMII0\_CONN\_TX\_M

SGMII1\_RX\_M

84

24

SGMII0\_INT\_MDPX3\_1P8\_N

SGMII1\_TX\_P

85

25

SGMII0\_RST\_MDPX3\_1P8\_N

SGMII1\_TX\_M

86

26

MD\_GPIO\_13\_MDPX3\_1P8

SGMII1\_INT\_MDPX3\_1P8\_N

87

27

MD\_GPIO\_14\_MDPX3\_1P8

SGMII1\_RST\_MDPX3\_1P8\_N

88

28

MD\_GPIO\_15\_MDPX3\_1P8

SAIL\_ERR0\_SPX3\_1P8

89

29

MD\_GPIO\_16\_MDPX3\_1P8

SAIL\_ERR1\_SPX3\_1P8

90

30

SAIL\_CAN0\_TX\_SPX3\_1P8

SAIL\_SPI\_MISO\_SPX3\_1P8

91

31

SAIL\_CAN0\_RX\_SPX3\_1P8

SAIL\_SPI\_MOSI\_SPX3\_1P8

92

32

SAIL\_CAN1\_TX\_SPX3\_1P8

SAIL\_SPI\_SCLK\_SPX3\_1P8

93

33

SAIL\_CAN1\_RX\_SPX3\_1P8

SAIL\_SPI\_CS\_0\_SPX3\_1P8

94

34

SAIL\_CAN2\_TX\_SPX3\_1P8

SAIL\_SPI\_CS\_1\_SPX3\_1P8

95

35

SAIL\_CAN2\_RX\_SPX3\_1P8

SAIL\_GPIO\_15\_SPX3\_1P8

96

36

SAIL\_CAN3\_TX\_SPX3\_1P8

SAIL\_GPIO\_16\_SPX3\_1P8

97

37

SAIL\_CAN3\_RX\_SPX3\_1P8

SAIL\_GPIO\_17\_SPX3\_1P8

98

38

SAIL\_CAN4\_TX\_SPX3\_1P8

SAIL\_GPIO\_18\_SPX3\_1P8

99

39

SAIL\_CAN4\_RX\_SPX3\_1P8

SAIL\_PMIC\_INT\_SPX3\_1P8\_N

100

40

SAIL\_CAN5\_TX\_SPX3\_1P8

SAIL\_INT\_SPX3\_1P8\_N

101

41

SAIL\_CAN5\_RX\_SPX3\_1P8

SAIL\_PWR\_READY\_SPX3\_1P8

102

42

SAIL\_CAN6\_TX\_SPX3\_1P8

SAIL\_SLP\_EN\_SPX3\_1P8

103

43

SAIL\_CAN6\_RX\_SPX3\_1P8

SAIL\_DBG\_UART\_TX\_SPX3\_1P8

104

44

SAIL\_CAN7\_TX\_SPX3\_1P8

SAIL\_DBG\_UART\_RX\_SPX3\_1P8

105

45

SAIL\_CAN7\_RX\_SPX3\_1P8

GND

106

46

SAIL\_CAN\_INT0\_SPX3\_1P8

PCIE0\_MEZZCONN\_CLK\_P

107

47

SAIL\_CAN\_INT1\_SPX3\_1P8

PCIE0\_MEZZCONN\_CLK\_N

108

48

SAIL\_CAN\_STB\_0\_SPX3\_1P8

GND

109

49

SAIL\_CAN\_STB\_1\_SPX3\_1P8

PCIE0\_MEZZCONN\_RX0\_P

110

50

SAIL\_CAN\_STB\_2\_SPX3\_1P8

PCIE0\_MEZZCONN\_RX0\_N

111

51

SAIL\_CAN\_STB\_3\_SPX3\_1P8

GND

112

52

SAIL\_CAN6\_CTL\_SPX3\_1P8

PCIE0\_MEZZCONN\_RX1\_P

113

53

SAIL\_CAN7\_CTL\_SPX3\_1P8

PCIE0\_MEZZCONN\_RX1\_N

114

54

SAIL\_CAN8\_CTL\_SPX3\_1P8

GND

115

55

PCIE0\_MEZZCONN\_RST\_1P8\_N

PCIE0\_MEZZCONN\_TX0\_P

116

56

PCIE0\_MEZZCONN\_CLKREQ\_1P8\_N

PCIE0\_MEZZCONN\_TX0\_N

117

57

PCIE0\_MEZZCONN\_WAKE\_1P8\_N

GND

118

58

PMG\_GPIO\_3\_GNSS\_RESET\_1P8

PCIE0\_MEZZCONN\_TX1\_P

119

59

PMG\_GPIO\_4\_GNSS\_EN\_1P8

PCIE0\_MEZZCONN\_TX1\_N

120

60

PMG\_GPIO\_5\_GNSS\_BOOT\_MODE\_1P8

The following table details the pin mapping for the JEXP2 connector.

Table : Pin mapping for the JEXP2 connector

Pin name

Pin number

Pin number

Pin name

VREG\_MDPX3\_1P8

61

1

VREG\_SPX3\_1P8

GND

62

2

GND

SOC\_MI2S\_MCLK0\_MDPX3\_1P8

63

3

VREG\_SPX8

SOC\_MI2S1\_SCK\_MDPX3\_1P8

64

4

GND

SOC\_MI2S1\_WS\_MDPX3\_1P8

65

5

USB01\_I2C\_SDA\_MDPX3\_1P8

SOC\_MI2S1\_DATA0\_MDPX3\_1P8

66

6

USB01\_I2C\_SCL\_MDPX3\_1P8

SOC\_MI2S1\_DATA1\_MDPX3\_1P8

67

7

VREG\_1P8\_EN

MI2S2\_SCK\_MDPX3\_1P8

68

8

VREG\_1P2\_EN

MI2S2\_WS\_MDPX3\_1P8

69

9

USB\_VBUS\_DET\_MDPX3\_1P8

MI2S2\_DATA0\_MDPX3\_1P8

70

10

USB\_RESET\_MDPX3\_1P8\_N

MI2S2\_DATA1\_MDPX3\_1P8

71

11

USB1\_ID\_MDPX3\_1P8

HS0\_MI2S\_SCK\_CONN

72

12

USB0\_ID\_MDPX3\_1P8

HS0\_MI2S\_WS\_CONN

73

13

PMG\_GPIO\_8

HS0\_MI2S\_DATA0\_CONN

74

14

PME\_GPIO\_7\_SENSOR\_RST\_1P8

HS0\_MI2S\_DATA1\_CONN

75

15

PME\_GPIO\_6\_USB1\_INT\_3P3\_N

HS1\_MI2S\_SCK\_CONN

76

16

PME\_GPIO\_5\_USB0\_INT\_3P3\_N

HS1\_MI2S\_WS\_CONN

77

17

MD\_GPIO\_70\_MDPX3\_1P8

HS1\_MI2S\_DATA0\_CONN

78

18

EXP\_I2C\_SDA\_MDPX3\_1P8

HS1\_MI2S\_DATA1\_CONN

79

19

EXP\_I2C\_SCL\_MDPX3\_1P8

HS2\_MI2S\_SCK\_CONN

80

20

FAN\_INT\_MDPX3\_1P8\_N

HS2\_MI2S\_WS\_CONN

81

21

HUB\_P2\_USB\_HS\_P

HS2\_MI2S\_DATA0\_CONN

82

22

HUB\_P2\_USB\_HS\_M

HS2\_MI2S\_DATA1\_CONN

83

23

HUB\_P2\_USB\_SS\_RX\_P

SOC\_QUA\_MI2S\_SCK\_MDPX3\_1P8

84

24

HUB\_P2\_USB\_SS\_RX\_M

SOC\_QUA\_MI2S\_WS\_MDPX3\_1P8

85

25

HUB\_P2\_USB\_SS\_TX\_P

SOC\_QUA\_MI2S\_DATA0\_MDPX3\_1P8

86

26

HUB\_P2\_USB\_SS\_TX\_M

SOC\_QUA\_MI2S\_DATA1\_MDPX3\_1P8

87

27

GND

SOC\_QUA\_MI2S\_DATA2\_MDPX3\_1P8

88

28

HUB\_P3\_USB\_HS\_M

SOC\_QUA\_MI2S\_DATA3\_MDPX3\_1P8

89

29

HUB\_P3\_USB\_HS\_P

SOC\_I2S1\_SCK\_MDPX3\_1P8

90

30

HUB\_P3\_USB\_SS\_TX\_P

SOC\_I2S1\_WS\_MDPX3\_1P8

91

31

HUB\_P3\_USB\_SS\_TX\_M

SOC\_I2S1\_DATA0\_MDPX3\_1P8

92

32

HUB\_P3\_USB\_SS\_RX\_P

SOC\_I2S1\_DATA1\_MDPX3\_1P8

93

33

HUB\_P3\_USB\_SS\_RX\_M

I2S2\_CLK\_MDPX3\_1P8

94

34

GND

I2S2\_WS\_MDPX3\_1P8

95

35

HUB\_P4\_USB\_HS\_M

I2S2\_DATA0\_MDPX3\_1P8

96

36

HUB\_P4\_USB\_HS\_P

I2S2\_DATA1\_MDPX3\_1P8

97

37

HUB\_P4\_USB\_SS\_TX\_P

SOC\_I2S3\_SCK\_MDPX3\_1P8

98

38

HUB\_P4\_USB\_SS\_TX\_M

SOC\_I2S3\_WS\_MDPX3\_1P8

99

39

HUB\_P4\_USB\_SS\_RX\_P

SOC\_I2S3\_DATA0\_MDPX3\_1P8

100

40

HUB\_P4\_USB\_SS\_RX\_M

SOC\_I2S3\_DATA1\_MDPX3\_1P8

101

41

GND

I2S4\_SCK\_MDPX3\_1P8

102

42

SAIL\_RGMII\_RESET\_SPX8\_N

I2S4\_WS\_MDPX3\_1P8

103

43

SAIL\_RGMII\_INT\_SPX8\_N

I2S4\_DATA0\_MDPX3\_1P8

104

44

SAIL\_RGMII\_MDIO\_SPX8

I2S4\_DATA1\_MDPX3\_1P8

105

45

SAIL\_RGMII\_MDC\_SPX8

SAIL\_CONN\_OSPI0\_CS0\_SPX3\_1P8\_N

106

46

SAIL\_RGMII\_RX\_CTL\_SPX8

SAIL\_CONN\_OSPI0\_DQS\_SPX3\_1P9

107

47

SAIL\_RGMII\_RXC\_SPX8

SAIL\_CONN\_OSPI0\_WR\_SPX3\_1P8\_N

108

48

SAIL\_RGMII\_RXD0\_SPX8

SAIL\_CONN\_OSPI0\_CLK\_SPX3\_1P9

109

49

SAIL\_RGMII\_RXD1\_SPX8

SAIL\_CONN\_OSPI0\_DATA\_0\_SPX3\_1P9

110

50

SAIL\_RGMII\_RXD2\_SPX8

SAIL\_CONN\_OSPI0\_DATA\_1\_SPX3\_1P9

111

51

SAIL\_RGMII\_RXD3\_SPX8

SAIL\_CONN\_OSPI0\_DATA\_2\_SPX3\_1P9

112

52

SAIL\_RGMII\_TX\_CTL\_SPX8

SAIL\_CONN\_OSPI0\_DATA\_3\_SPX3\_1P9

113

53

SAIL\_RGMII\_TXC\_SPX8

SAIL\_CONN\_OSPI0\_DATA\_4\_SPX3\_1P9

114

54

SAIL\_RGMII\_TXD0\_SPX8

SAIL\_CONN\_OSPI0\_DATA\_5\_SPX3\_1P9

115

55

SAIL\_RGMII\_TXD1\_SPX8

SAIL\_CONN\_OSPI0\_DATA\_6\_SPX3\_1P9

116

56

SAIL\_RGMII\_TXD2\_SPX8

SAIL\_CONN\_OSPI0\_DATA\_7\_SPX3\_1P9

117

57

SAIL\_RGMII\_TXD3\_SPX8

SAIL\_RESOUT\_SPX3\_1P8\_N

118

58

GND

MD\_GPIO\_34\_MDPX3\_1P8

119

59

VREG\_5P0

MD\_GPIO\_35\_MDPX3\_1P8

120

60

VREG\_5P0

The following table details the pin mapping for the JEXP3 connector.

Table : Pin mapping for the JEXP3 connector

Pin name

Pin number

Pin number

Pin name

MD\_GPIO\_52\_MDPX3\_1P8

61

1

EDP2\_LN0\_P

MD\_GPIO\_53\_MDPX3\_1P8

62

2

EDP2\_LN0\_M

MD\_GPIO\_54\_MDPX3\_1P8

63

3

GND

MD\_GPIO\_55\_MDPX3\_1P8

64

4

EDP2\_LN1\_P

MD\_RESOUT\_MDPX3\_1P8\_N

65

5

EDP2\_LN1\_M

PMC\_GPIO\_7\_WLAN\_EN\_1P8

66

6

GND

HST\_SW\_CTRL\_MDPX3\_1P8

67

7

EDP2\_LN2\_P

PMC\_GPIO\_8\_BT\_EN\_1P8

68

8

EDP2\_LN2\_M

BT0\_UART\_CTS\_MDPX3\_1P8

69

9

GND

BT0\_UART\_RFR\_MDPX3\_1P8

70

10

EDP2\_LN3\_P

BT0\_UART\_TX\_MDPX3\_1P8

71

11

EDP2\_LN3\_M

BT0\_UART\_RX\_MDPX3\_1P8

72

12

GND

MD\_GPIO\_28\_MDPX3\_1P8

73

13

EDP2\_AUX\_P

MD\_GPIO\_29\_MDPX3\_1P8

TPM\_SPI\_PIRQ

74

14

EDP2\_AUX\_M

BTLE\_UART\_TX\_MDPX3\_1P8

75

15

GND

BTLE\_UART\_RX\_MDPX3\_1P8

76

16

EDP3\_LN0\_P

VREG\_L8C\_UFS1

77

17

EDP3\_LN0\_M

GND

78

18

GND

DSI1\_A0\_LN0\_P

79

19

EDP3\_LN1\_P

DSI1\_A0\_LN0\_M

80

20

EDP3\_LN1\_M

GND

81

21

GND

DSI1\_C0\_LN1\_P

82

22

EDP3\_LN2\_P

DSI1\_A1\_LN1\_M

83

23

EDP3\_LN2\_M

GND

84

24

GND

DSI1\_B1\_CLK\_P

85

25

EDP3\_LN3\_P

DSI1\_C1\_CLK\_M

86

26

EDP3\_LN3\_M

GND

87

27

GND

DSI1\_A2\_LN2\_P

88

28

EDP3\_AUX\_P

DSI1\_B2\_LN2\_M

89

29

EDP3\_AUX\_M

GND

90

30

MDP\_VSYNC\_MDPX3\_1P8

DSI1\_C2\_LN3\_P

91

31

VREG\_5P0\_PGOOD

DSI1\_NC\_LN3\_M

92

32

PG\_VREG\_3P3\_SIP

GND

93

33

EDP2\_HPD\_MDPX3\_1P8

PMC\_GPIO\_4\_IPA\_PWR\_EN\_1P8

94

34

EDP3\_HPD\_MDPX3\_1P8

PMC\_GPIO\_5\_WLAN\_PWR\_EN2\_1P8

95

35

MD\_GPIO\_78\_MDPX3\_1P8

PMC\_GPIO\_6\_WLAN\_DBU4\_EN\_1P8

96

36

DISP\_RST\_MDPX3\_1P8\_N

PMC\_GPIO\_11\_WLAN\_EN2\_1P8

97

37

DISP\_INT\_MDPX3\_1P8\_N

PMC\_GPIO\_12\_BT\_EN2\_1P8

98

38

MD\_GPIO\_76\_MDPX3\_1P8

MD\_GPIO\_79\_MDPX3\_1P8

99

39

LCD\_RESET\_MDPX3\_1P8

SENSOR\_I2C\_SDA\_MDPX3\_1P8

100

40

MD\_GPIO\_40\_MDPX3\_1P8

SENSOR\_I2C\_SCL\_MDPX3\_1P8

101

41

MD\_GPIO\_41\_MDPX3\_1P8

MD\_GPIO\_84\_MDPX3\_1P8

102

42

MD\_GPIO\_42\_MDPX3\_1P8

MD\_GPIO\_85\_MDPX3\_1P8

103

43

MD\_GPIO\_43\_MDPX3\_1P8

MD\_GPIO\_86\_MDPX3\_1P8

104

44

MD\_GPIO\_44\_MDPX3\_1P8

MD\_GPIO\_87\_MDPX3\_1P8

105

45

MD\_GPIO\_45\_MDPX3\_1P8

MD\_GPIO\_88\_MDPX3\_1P8

106

46

PMS\_GPIO\_4\_USB0\_VBUS\_ON

MD\_GPIO\_89\_MDPX3\_1P8

107

47

MD\_GPIO\_10\_MDPX3\_1P8

MD\_GPIO\_90\_MDPX3\_1P8

108

48

SENSOR\_SLP\_CLK\_MDPX3\_1P8

MD\_GPIO\_140\_MDPX3\_1P8

109

49

DISP\_I2C\_SDA\_MDPX3\_1P8

MD\_GPIO\_77\_MDPX3\_1P8

110

50

DISP\_I2C\_SCL\_MDPX3\_1P8

MD\_DBG\_UART\_TX\_MDPX3\_1P8

111

51

MD\_GPIO\_20\_MDPX3\_1P8

MD\_DBG\_UART\_RX\_MDPX3\_1P8

112

52

MD\_GPIO\_21\_MDPX3\_1P8

MD\_GPIO\_56\_MDPX3\_1P8

113

53

MD\_GPIO\_22\_MDPX3\_1P8

MD\_GPIO\_57\_MDPX3\_1P8

114

54

MD\_GPIO\_23\_MDPX3\_1P8

PMA\_GPIO\_02\_POFF\_COMPLETE\_3P3\_N

115

55

MD\_GPIO\_36\_MDPX3\_1P8

PMA\_GPIO\_06\_AOSS\_SLP\_ENT\_3P3

116

56

MD\_GPIO\_37\_MDPX3\_1P8

VREG\_S5A\_WLAN\_BT\_1P95

117

57

MD\_GPIO\_38\_MDPX3\_1P8

VREG\_L2C\_WLAN\_BT\_1P05

118

58

IOEXPAN3\_INT\_MDPX3\_1P8\_N

VREG\_L6E\_WLAN\_BT\_1P35

119

59

MD\_GPIO\_71\_MDPX3\_1P8

PMS\_GPIO\_8\_USB1\_VBUS\_ON

120

60

MD\_GPIO\_69\_MDPX3\_1P8

The following table details the pin mapping for the JEXP4 connector.

Table : Pin mapping for the JEXP4 connector

Pin name

Pin number

Pin number

Pin name

SDIO\_EMMC\_CMD\_MDPX7\_1P8

61

1

PCIE2USB\_PWR\_EN\_1P8

SDIO\_EMMC\_CLK\_MDPX7\_1P8

62

2

PCIE1\_MEZZCONN\_CLK\_N

SDIO\_EMMC\_RCLK\_MDPX7\_1P8

63

3

PCIE1\_MEZZCONN\_CLK\_P

SDIO\_EMMC\_DATA\_7\_MDPX7\_1P8

64

4

GND

SDIO\_EMMC\_DATA\_6\_MDPX7\_1P8

65

5

PCIE1\_MEZZCONN\_RX0\_N

SDIO\_EMMC\_DATA\_5\_MDPX7\_1P8

66

6

PCIE1\_MEZZCONN\_RX0\_P

SDIO\_EMMC\_DATA\_4\_MDPX7\_1P8

67

7

GND

SDIO\_EMMC\_DATA\_3\_MDPX7\_1P8

68

8

PCIE1\_MEZZCONN\_RX1\_N

SDIO\_EMMC\_DATA\_2\_MDPX7\_1P8

69

9

PCIE1\_MEZZCONN\_RX1\_P

SDIO\_EMMC\_DATA\_1\_MDPX7\_1P8

70

10

GND

SDIO\_EMMC\_DATA\_0\_MDPX7\_1P8

71

11

PCIE1\_MEZZCONN\_RX2\_N

MD\_GPIO\_68\_MDPX3\_1P8

72

12

PCIE1\_MEZZCONN\_RX2\_P

PCIE\_SWITCH\_PWR\_EN\_1P8

73

13

GND

PCIE2USB\_RST\_MDPX3\_1P8\_N

74

14

PCIE1\_MEZZCONN\_RX3\_N

PCIE1\_MEZZCONN\_RST\_1P8\_N

75

15

PCIE1\_MEZZCONN\_RX3\_P

PCIE1\_MEZZCONN\_CLKREQ\_1P8\_N

76

16

GND

PCIE1\_MEZZCONN\_WAKE\_1P8\_N

77

17

PCIE1\_MEZZCONN\_TX0\_N

CAM3\_PWR\_EN\_MDPX3\_1P8

78

18

PCIE1\_MEZZCONN\_TX0\_P

PME\_GPIO\_11\_USB2\_ID

79

19

GND

CCI6\_I2C\_SDA\_MDPX3\_1P8

80

20

PCIE1\_MEZZCONN\_TX1\_N

CCI6\_I2C\_SCL\_MDPX3\_1P8

81

21

PCIE1\_MEZZCONN\_TX1\_P

CAM3\_MCLK\_MDPX3\_1P8

82

22

GND

CAM3\_PWDN\_MDPX3\_1P8

83

23

PCIE1\_MEZZCONN\_TX2\_N

CAM3\_STROBE\_MDPX3\_1P8

84

24

PCIE1\_MEZZCONN\_TX2\_P

CAM3\_SPARE\_GPIO\_MDPX3\_1P8

85

25

GND

CAM2\_PWR\_EN\_MDPX3\_1P8

86

26

PCIE1\_MEZZCONN\_TX3\_N

PME\_GPIO\_10\_USB1\_PWR\_EN\_1P8

87

27

PCIE1\_MEZZCONN\_TX3\_P

CCI4\_I2C\_SDA\_MDPX3\_1P8

88

28

GND

CCI4\_I2C\_SCL\_MDPX3\_1P8

89

29

CSI3\_CONN\_NC\_CLK\_P

CAM2\_MCLK\_MDPX3\_1P8

90

30

CSI3\_CONN\_A0\_CLK\_M

CAM2\_PWDN\_MDPX3\_1P8

91

31

CSI3\_CONN\_B0\_LN0\_P

CAM2\_STROBE\_MDPX3\_1P8

92

32

CSI3\_CONN\_C0\_LN0\_M

CAM2\_SPARE\_GPIO\_MDPX3\_1P8

93

33

CSI3\_CONN\_A1\_LN1\_P

CAM1\_PWR\_EN\_MDPX3\_1P8

94

34

CSI3\_CONN\_B1\_LN1\_M

MD\_GPIO\_12\_MDPX3\_1P8

95

35

CSI3\_CONN\_C1\_LN2\_P

CCI2\_I2C\_SDA\_MDPX3\_1P8

96

36

CSI3\_CONN\_A2\_LN2\_M

CCI2\_I2C\_SCL\_MDPX3\_1P8

97

37

CSI3\_CONN\_B2\_LN3\_P

CAM1\_MCLK\_MDPX3\_1P8

98

38

CSI3\_CONN\_C2\_LN3\_M

CAM1\_PWDN\_MDPX3\_1P8

99

39

GND

CAM1\_STROBE\_MDPX3\_1P8

100

40

CSI2\_CONN\_NC\_CLK\_P

CAM1\_SPARE\_GPIO\_MDPX3\_1P8

101

41

CSI2\_CONN\_A0\_CLK\_M

CAM0\_PWR\_EN\_MDPX3\_1P8

102

42

CSI2\_CONN\_B0\_LN0\_P

MD\_GPIO\_11\_MDPX3\_1P8

103

43

CSI2\_CONN\_C0\_LN0\_M

CCI0\_I2C\_SDA\_MDPX3\_1P8

104

44

CSI2\_CONN\_A1\_LN1\_P

CCI0\_I2C\_SCL\_MDPX3\_1P8

105

45

CSI2\_CONN\_B1\_LN1\_M

CAM0\_MCLK\_MDPX3\_1P8

106

46

CSI2\_CONN\_C1\_LN2\_P

CAM0\_PWDN\_MDPX3\_1P8

107

47

CSI2\_CONN\_A2\_LN2\_M

CAM0\_STROBE\_MDPX3\_1P8

108

48

CSI2\_CONN\_B2\_LN3\_P

CAM0\_SPARE\_GPIO\_MDPX3\_1P8

109

49

CSI2\_CONN\_C2\_LN3\_M

GND

110

50

GND

CSI0\_CONN\_NC\_CLK\_P

111

51

CSI1\_CONN\_NC\_CLK\_P

CSI0\_CONN\_A0\_CLK\_M

112

52

CSI1\_CONN\_A0\_CLK\_M

CSI0\_CONN\_B0\_LN0\_P

113

53

CSI1\_CONN\_B0\_LN0\_P

CSI0\_CONN\_C0\_LN0\_M

114

54

CSI1\_CONN\_C0\_LN0\_M

CSI0\_CONN\_A1\_LN1\_P

115

55

CSI1\_CONN\_A1\_LN1\_P

CSI0\_CONN\_B1\_LN1\_M

116

56

CSI1\_CONN\_B1\_LN1\_M

CSI0\_CONN\_C1\_LN2\_P

117

57

CSI1\_CONN\_C1\_LN2\_P

CSI0\_CONN\_A2\_LN2\_M

118

58

CSI1\_CONN\_A2\_LN2\_M

CSI0\_CONN\_B2\_LN3\_P

119

59

CSI1\_CONN\_B2\_LN3\_P

CSI0\_CONN\_C2\_LN3\_M

120

60

CSI1\_CONN\_C2\_LN3\_M

Low speed header

In the Dragonwing IQ-9075, there’s one low speed connector (JLS1, 87381-4063) that provides access to various GPIOs, CAN, QUPs, and other interfaces. For the position of this connector, see the Connectors on Dragonwing IQ-9075 EVK.

The following table details the pin mapping for the JLS1 connector

Table : Pin mapping for the JLS1 connector

Pin name

Pin number

Pin number

Pin name

GND

1

2

GND

MD\_GPIO\_52\_3P3 (UART CTS)

3

4

CAN\_H

MD\_GPIO\_54\_3P3 (UART TX)

5

6

CAN\_L

MD\_GPIO\_55\_3P3 (UART RX)

7

8

MD\_GPIO\_32\_3P3 (SPI MISO)

MD\_GPIO\_53\_3P3 (UART RFR)

9

10

MD\_GPIO\_33\_3P3 (SPI MOSI)

MD\_GPIO\_44\_3P3 (UART TX)

11

12

MD\_GPIO\_34\_3P3 (SPI CLK)

MD\_GPIO\_45\_3P3 (UART RX)

13

14

MD\_GPIO\_35\_3P3 (SPI CS)

EXP\_I2C\_SCL\_3P3 (GPIO 95)

15

16

SOC\_MI2S1\_WS\_3P3

EXP\_I2C\_SDA\_3P3 (GPIO 96)

17

18

SOC\_MI2S1\_SCK\_3P3

SENSOR\_I2C\_SCL\_3P3

19

20

SOC\_MI2S1\_DATA1\_3P3

SENSOR\_I2C\_SDA\_3P3

21

22

SOC\_MI2S1\_DATA0\_3P3

MD\_GPIO\_40\_3P3 (UART CTS)

23

24

SOC\_MI2S\_MCLK0\_3P3

MD\_GPIO\_41\_3P3 (UART RFR)

25

26

MD\_GPIO\_43\_3P3 (UART RX)

MD\_GPIO\_42\_3P3 (UART TX)

27

28

SAIL\_GP1\_CLK\_A\_3P3

PME\_GPIO\_11\_USB2\_ID

29

30

SAIL\_GP3\_CLK\_A\_3P3

MD\_GPIO\_140\_3P3

31

32

SAIL\_GP4\_CLK\_A\_3P3

IOEXPAN3\_GPIO\_7\_3P3

33

34

SAIL\_GP5\_CLK\_A\_3P3

VREG\_3P3\_SIP

35

36

VREG\_SYSTEM\_PWR

VREG\_5P0

37

38

VREG\_SYSTEM\_PWR

GND

39

40

GND

Debug interface

The platform includes a micro-USB connector receptacle (JTAC, part number: 0475890001) connected to an FTDI chip (U19, part number: FT4232HL-REEL), which is used for debugging purposes.

For the location of the debug interface connector on the platform, see the Connectors on Dragonwing IQ-9075 EVK.

JTAG interface

The JTAG connector header on the board is a 20-position pin interconnect with a 0.050” (1.27 mm) pitch and 0.050” (1.27 mm) row spacing. The reference designator for the JTAG connector component is JTAG, and its part number is FTSH-110-01-L-D-RA-K. To use a traditional JTAG connector, an adapter such as the 65-PM339-1 may be required.

For the location of the JTAG connectors on the platform, see the Connectors on Dragonwing IQ-9075 EVK.

Audio

For speaker and audio support, the HS0\_MI2S interface is used for the two onboard audio amplifiers, and the HS2\_MI2S interface is used for the I2S microphone on the mainboard. Both interfaces can optionally be switched to the mezzanine connectors for expansion purposes.

Consider the following details about speakers and microphones on the device:

Speakers: Onboard speakers (with MAX98357 I2S-amps); HS0\_MI2S is shared between both left and right speakers to enable stereo sound.

Microphones: The EVK includes a single onboard microphone (MMICT5848) that uses the HS2\_MI2S interface. By default, the microphone is configured to the left channel. To switch the microphone to the right channel, rework or move resistor R180 to R179 location. For more information about the location of resistor, see the Design Package, IQ-9075 EVK Design Files (DP25-73418-42).

The following figure shows the audio interfaces and configuration.

Third-party

Connectors

Primary interfacesignals

Control / Power/ Auxiliary signals

Qualcomm

IQ-9075M SoC

U7

JEXP2

JSPKR

MEMSmicrophone

120-pinB2B expansionconnector

Surfacemount 4-pin connector

GPIO\_114/115/116/117

GPIO\_95/96

S10

U34

U35

GM1

AB switch

U69

GPIO Expander

SEL

I2Caddr:0x39

P4

Dx

SxA

SxB

HS0\_MI2S

HS0\_MI2S\_CONN

SPK\_SEL

GPIO\_118/119/120/121

S11

AB switch

SEL

Dx

SxA

SxB

HS1\_MI2S

HS1\_MI2S

SPK\_SEL

GPIO\_122/123/124/125

S12

AB switch

SEL

Dx

SxA

SxB

HS2\_MI2S

HS2\_MI2S

HS2\_MI2S

SEL

SPKR\_OUT\_L

SPKR\_OUT\_R

Audioamplifier

HS1\_MI2S

Audioamplifier

HS0\_MI2S

U68

I2C\_SDA/SCL

I2C\_SDA/SCL

GPIO Expander

I2Caddr:0x38

P7

Figure : Audio interfaces and configuration

The following figure shows the Dragonwing IQ-9075 EVK connected to two mini speakers.

../../\_images/speakers-connected.png

Figure : Dragonwing IQ-9075 EVK connected to two mini speakers

Thermal management and fan control

The Dragonwing IQ-9075 EVK is designed to consume up to 70 W, necessitating a substantial thermal solution. The default cooling solution is fan-based, which uses a CPU cooler mounted to the bottom of the device.

The following figures show the thermal management solutions implemented in the Dragonwing IQ-9075 EVK. The fan controller used on this board is a Texas Instruments AMC6821SQDBQRQ1 PWM fan controller IC. The fan used in the system is connected using JFAN connector (S6B-XH-SM4-TB(LF)(SN)) on the mainboard.

Future versions of the device may offer different thermal options, including smaller fans or heatsinks, depending on the expected use cases.

../../\_images/thermal-management-on-iq9075-evk.png

Figure : Thermal management on Dragonwing IQ-9075 EVK

Accessory boards

This information will be provided in a future revision of the document.

Next steps

Set up the device.

Run sample applications.

Develop an application.