> ## Documentation Index
> Fetch the complete documentation index at: https://dragonwingdocs.qualcomm.com/llms.txt
> Use this file to discover all available pages before exploring further.

# RTSS interfaces overview

[QUP v3](https://dragonwingdocs.qualcomm.com/System/Interfaces/references) is a flexible and programmable module for supporting a wide range of serial interfaces such as [I2C](https://dragonwingdocs.qualcomm.com/System/Interfaces/i2-c), [SPI](https://dragonwingdocs.qualcomm.com/System/Interfaces/spi), and [UART](https://dragonwingdocs.qualcomm.com/System/Interfaces/uart).

The table lists the default QUP configurations on the device:

|    **RTSS QUP**   | **Protocol** | **Qualcomm Dragonwing<sup>TM</sup> IQ-9075 pins** | **Qualcomm Dragonwing<sup>TM</sup> IQ-8275 pins** |
| :---------------: | :----------: | :-----------------------------------------------: | :-----------------------------------------------: |
| RTSS\_QUP0\_SE\_0 |     i2c0     |                        0, 1                       |                        0, 1                       |
| RTSS\_QUP0\_SE\_2 |  uart1 Debug |                        6, 7                       |                        8, 9                       |
| RTSS\_QUP0\_SE\_3 |     i2c1     |                        8, 9                       |                       10, 11                      |
| RTSS\_QUP0\_SE\_4 |   spi0/can   |                 10, 11, 12, 13, 14                |                 14, 15, 16, 17, 18                |

RTSS has five RTSS\_QUP serial engines (SEs). Each QUP SE has up to seven lanes (I/O) numbered from 0 to 6. You can select only one protocol for one QUP SE at a time. For example, RTSS doesn’t support simultaneous UART and I<sup>2</sup>C functionality.

The supported assignments are listed in the table for each QUP:

<Tabs>
  <Tab title="IQ-9075">
    The following tables provide information about the RTSS\_QUP assignments and QUP lane to RTSS I/O mapping:

    | **RTSS QUP core instance (tile)** | **Serial engine** | **UART (64 B FIFO)** | **HS UART (128 B FIFO)** | **I<sup>2</sup>C controller** | **SPI controller** | **SPI target** | **QUP lane to RTSS I/O mapping** |    |    |    |   |   |   |
    | :-------------------------------: | :---------------: | :------------------: | :----------------------: | :---------------------------: | :----------------: | :------------: | :------------------------------: | -- | -- | -- | - | - | - |
    |               **L0**              |       **L1**      |        **L2**        |          **L3**          |             **L4**            |       **L5**       |     **L6**     |                                  |    |    |    |   |   |   |
    |             RTSS\_QUP0            | RTSS\_QUP0\_SE\_0 |          Yes         |             –            |              Yes              |         Yes        |       Yes      |                 0                | 1  | 6  | 7  | – | – | – |
    |         RTSS\_QUP0\_SE\_2         |        Yes        |          Yes         |            Yes           |              Yes              |          –         |        8       |                 9                | 6  | 7  | –  | – | – |   |
    |         RTSS\_QUP0\_SE\_3         |        Yes        |          Yes         |            Yes           |              Yes              |          –         |        8       |                 9                | 4  | 5  | –  | – | – |   |
    |         RTSS\_QUP0\_SE\_4         |        Yes        |           –          |            Yes           |              Yes              |          –         |       10       |                11                | 12 | 13 | 14 | – | – |   |
  </Tab>

  <Tab title="IQ-8275">
    The following tables provide information about the RTSS\_QUP assignments and QUP lane to RTSS I/O mapping:

    | **RTSS QUP core instance (tile)** | **Serial engine** | **UART (64 B FIFO)** | **HS UART (128 B FIFO)** | **I<sup>2</sup>C controller** | **SPI controller** | **SPI target** | **QUP lane to RTSS I/O mapping** |    |    |    |   |   |
    | :-------------------------------: | :---------------: | :------------------: | :----------------------: | :---------------------------: | :----------------: | :------------: | :------------------------------: | -- | -- | -- | - | - |
    |               **L0**              |       **L1**      |        **L2**        |          **L3**          |             **L4**            |       **L5**       |                |                                  |    |    |    |   |   |
    |                QUP0               |    QUP0\_SE\_0    |          Yes         |             –            |              Yes              |         Yes        |       Yes      |                 0                | 1  | 2  | 3  | – | – |
    |            QUP0\_SE\_2            |        Yes        |          Yes         |            Yes           |              Yes              |          –         |       12       |                13                | 8  | 9  | –  | – |   |
    |            QUP0\_SE\_3            |        Yes        |          Yes         |            Yes           |              Yes              |          –         |       10       |                11                | 12 | 13 | –  | – |   |
    |            QUP0\_SE\_4            |        Yes        |           –          |            Yes           |              Yes              |          –         |       14       |                15                | 16 | 17 | 18 | – |   |
  </Tab>
</Tabs>

## **QUP v3 serial engine customization**

All serial engines in QUP v3 can be configured to specific interfaces such as I<sup>2</sup>C, UART, or SPI. The following use case defines the default protocol assigned to each enabled serial engine. You can modify the configuration based on board design.

```undefined theme={null}
aliases {
  i2c0   = &se0_i2c;
  uart0  = &se1_uart;
  uart1  = &se2_uart;
  i2c1   = &se3_i2c;
  spi0   = &se4_spi;
  ospi0  = &spinor_monaco;
  ospi1  = &spinor_lemans;
};
```

If SE0 is enabled by default as an I<sup>2</sup>C interface, you can reconfigure it as SPI by updating the aliases as shown in the following example:

```cpp theme={null}
aliases {
    uart0  = &se1_uart;     //remove i2c0
    uart1  = &se2_uart;
    i2c1   = &se3_i2c;
    spi0   = &se4_spi;
    spi1   = &se0_spi;     //add spi1
    ospi0  = &spinor_monaco;
    ospi1  = &spinor_lemans;
  };
```

* [UART](UART)
* [I2C](I2C)
* [SPI](SPI)