> ## Documentation Index
> Fetch the complete documentation index at: https://dragonwingdocs.qualcomm.com/llms.txt
> Use this file to discover all available pages before exploring further.

# Configure DVFS governors

Qualcomm<sup>®</sup> Linux uses dynamic voltage and frequency scaling (DVFS) to balance power and performance. CPU frequency governors control the active CPU OPP; BWMON governors manage LLCC and DDR frequency based on measured bus traffic.

## Select the CPU DVFS governors

You can select a governor to tune the system for power or performance while changing the `CPUfreq` governor (`powersave/performance/schedutil`). By default, the CPU frequency governor is set to `performance` on Qualcomm<sup>®</sup> Linux kernel.

**Table: CPU DVFS variables**

|    **Variable**    |                **Description**                |                                    **Path**                                   |
| :----------------: | :-------------------------------------------: | :---------------------------------------------------------------------------: |
|  scaling\_governor |        Set the governor to performance.       | echo performance > /sys/devices/system/cpu/cpufreq/policy\*/scaling\_governor |
| scaling\_max\_freq | Set the maximum frequency of the CPU cluster. |          /sys/devices/system/cpu/cpufreq/policy\*/scaling\_max\_freq          |
| scaling\_min\_freq | Set the minimum frequency of the CPU cluster. |          /sys/devices/system/cpu/cpufreq/policy\*/scaling\_min\_freq          |

For more information about `CPUfreq`, see [CPU frequency and voltage scaling code in the Linux(TM) kernel](https://www.kernel.org/doc/Documentation/cpu-freq/governors.txt).

## Configure cache and memory DVFS governors

The static map DVFS governors align the CPU operating frequencies with the following:

* Level 3 cache (L3)
* Last level cache controller (LLCC)
* DDR RAM

If the CPU frequency is at the maximum level, either by setting the CPU frequency governor to performance, or due to load in the system, then the L3, LLCC, and DDR also run at their maximum frequencies.

The driver for this governor is present in the `drivers/cpufreq/qcom-cpufreq-hw.c` file, and static mapping is present in the `arch/arm64/boot/dts/qcom/sc7280.dtsi` file.

<Note>
  For Qualcomm SoCs, see the platform-specific DTSI files to get this information.
</Note>

The other bandwidth monitor (BWMON) governor is used to vote for LLCC and DDR frequencies, based on the measured traffic between CPU to LLCC and CPU to DDR. The driver for this governor is present in the `drivers/soc/qcom/icc-bwmon.c` file.

The mapping between **CPU frequency** and **L3/DDR frequency** is adjusted based on the power or performance requirements.

In DTSI, for each CPUx node, there is an `operating-points-v2 = <&cpux_opp_table>` entry. The `cpux_opp_table` holds a static mapping between CPU, L3, and DDR frequencies.

For example:

```text theme={null}
cpu0_opp_300mhz: opp-300000000 {
   opp-hz = /bits/ 64 <300000000>;
   opp-peak-kBps = <800000 9600000>;
};
```

When CPU 0 operates at 300 MHz, it votes for 9600000 Hz to L3, which translates to 300,000 Hz (9600000/w) L3 frequency. If the vote is for 800,000 Hz to DDR, this results in 200,000 Hz (800000 / w) DDR frequency.

In the equation, ‘w’ represents how many bytes can be written in a single cycle:

* For DDR, ‘w’ is 4 (each channel performs two transactions per cycle, with each transaction being 2 bytes).
* For L3, ‘w’ is 32 (one transaction per cycle at 32 bytes per transaction).

<Note>
  These values are set per channel for DDR, and the mapping relates CPU frequency to the memory controller (MC) channel bandwidth. Adjusting this map table can impact power and performance characteristics.
</Note>

For more information about the operating performance points (OPP) framework and syntax, see [Generic OPP (Operating Performance Points) Bindings](https://www.kernel.org/doc/Documentation/devicetree/bindings/opp/opp.txt).\\