> ## Documentation Index
> Fetch the complete documentation index at: https://dragonwingdocs.qualcomm.com/llms.txt
> Use this file to discover all available pages before exploring further.

#  MCU architecture overview

**5.1 MCU subsystem overview**

The MCU subsystem is optimized for event-driven execution, wake-latency-sensitive handling, local data qualification, and low-power autonomous processing.

<Frame caption="MCU subsystem (high-level view)">
  <img src="https://mintcdn.com/qualcomm-prod/_csx8xCfhr5Leh79/System/MCU-Application-Development/media/high-level-mcu-block-diagram.svg?fit=max&auto=format&n=_csx8xCfhr5Leh79&q=85&s=0e3c78b89ec9adb8189f1fc96459b455" alt="MCU subsystem (high-level view)" width="831" height="276" data-path="System/MCU-Application-Development/media/high-level-mcu-block-diagram.svg" />
</Frame>

**Figure 5-1 MCU subsystem (high-level view)**

The source positions it as a single 32-bit SiFive E61 RISC-V core with 16 KB instruction cache, 16 KB data cache, 128 KB L2 cache, 768 KB of local memory listed as TCM or DLS, 128 external interrupts plus NMI and a wake interrupt, a primary CX power domain, and a maximum frequency of up to 600 MHz

**Table 5-1 MCU subsystem attribute values**

| Attribute         | Description                                                   |
| ----------------- | ------------------------------------------------------------- |
| Core              | ▪ SiFive E61 <br />▪ Single 32-bit RISC-V core                |
| Caches            | ▪ 16 KB I-cache <br />▪ 16 KB D-cache <br />▪ 128 KB L2 cache |
| Local memory      | 768 KB TCM or DLS                                             |
| Interrupts        | 128 external interrupts plus NMI and wake interrupt           |
| Power domain      | Primary CX power domain                                       |
| Maximum frequency | Up to 600 MHz                                                 |

**5.2 Event-driven execution and wake model**

The MCU waits on a timer, interrupt, or peripheral event, executes a short service path, and returns to a low-cost idle state. External events route into MCU ISR handling through the interrupt infrastructure, with IRQ registration, wake-source classification, ISR-to-thread handoff, timer wake, GPIO wake, and UART receive activity all called out in the source.

**5.3 Platform services**

**Table 5-2 Platform services integration**

| Service                  | Integration view                                                                                                                       |
| ------------------------ | -------------------------------------------------------------------------------------------------------------------------------------- |
| QTIMER                   | ▪ Time base <br />▪ Deadline scheduling<br /> ▪ Delay measurement <br />▪ Low-power wake programing<br />▪ Bring-up timing validation. |
| Debug and trace          | ▪ Memory inspection <br />▪ Trace capture <br />▪ Register dumps <br />▪ Exception or fault triage                                     |
| Host interface           | ▪ Host signaling and acknowledgments when the MCU must communicate state or events upward.                                             |
| Power and resource hooks | ▪ Clock <br />▪ Rail <br />▪ Path dependencies asserted only for active work                                                           |