> ## Documentation Index
> Fetch the complete documentation index at: https://dragonwingdocs.qualcomm.com/llms.txt
> Use this file to discover all available pages before exploring further.

# Power architecture

The CPU subsystem architecture describes the organization of CPU cores and their power domains. Understanding the architecture helps you to monitor the CPU core usage and balance the power consumption and performance of the device.

<Tabs>
  <Tab title="QCS6490/QCS5430">
    APSS is a set of CPUs organized into clusters. All CPU cores in a cluster operate at a similar frequency. Each CPU core in a cluster has a dedicated L1 and L2 cache.

    The CPU subsystem consists of three clusters and L3 cache as follows:

    * Qualcomm<sup>®</sup> Kryo<sup>™</sup> CPU Prime cluster, which has a performance CPU core
    * Kryo Gold cluster, which has CPU cores with balanced power and performance
    * Kryo Silver cluster, which has low power CPU cores for lightweight applications
    * Common L3 cache

    <img src="https://mintcdn.com/qualcomm-prod/OKFyShYzKWv2bmj8/System/Power/media/k2c-perf/cpu_arch_qcs6490_updated_1.png?fit=max&auto=format&n=OKFyShYzKWv2bmj8&q=85&s=d7ac239b239c88583e4e9ca044bb4e7b" alt="IQ-8275 CPUSS Architecture" width="925" height="621" data-path="System/Power/media/k2c-perf/cpu_arch_qcs6490_updated_1.png" />

    **Figure : QCS6490/QCS5430 APSS CPU subsystem architecture**

    > > The CPU subsystem operates on two power domains, each supplied by a dedicated switched mode power supply (SMPS) rail.
    > > The following are the supported power domains:

    > |                   | **Table : Power domains and their descriptions**                           |
    > | ----------------- | -------------------------------------------------------------------------- |
    > | **Power domains** | **Description**                                                            |
    > | `VDD_APC0`        | Power domain for the Silver cluster CPU cores and L3 cache digital circuit |
    > | `VDD_APC1`        | Power domain for the Gold and Prime clusters CPU cores                     |
    > | `Chip_MX`         | Power domain for the L1, L2, and L3 cache memories                         |
    >
    > **Note**
    >
    > To know more about CPU core arrangement, see [QCS6490 Data Sheet](https://docs.qualcomm.com/bundle/publicresource/topics/80-23889-1/device-description.html) and [QCS5430 Data Sheet](https://docs.qualcomm.com/bundle/publicresource/topics/80-23889-1/device-description.html).
  </Tab>

  <Tab title="IQ-9075">
    The CPU subsystem consists of two clusters with a dedicated L3 cache for each cluster. Each CPU core in a cluster has a dedicated L1 and L2 cache. All CPU cores in a cluster operate at a similar frequency.

    <img src="https://mintcdn.com/qualcomm-prod/OKFyShYzKWv2bmj8/System/Power/media/k2c-perf/cpu_arch_qcs9075.png?fit=max&auto=format&n=OKFyShYzKWv2bmj8&q=85&s=c77b5e0a58ec6b4d08f09cff59ab05fd" alt="IQ-8275 CPUSS Architecture" width="922" height="646" data-path="System/Power/media/k2c-perf/cpu_arch_qcs9075.png" />

    **Figure : IQ-9075 APSS CPU subsystem architecture**

    > > The CPU subsystem operates on two power domains, each supplied by a dedicated SMPS rail.
    > >
    > > The following are the supported power domains:

    **Table : Power domains and their descriptions**

    | **Power domains** |                          **Description**                         |
    | :---------------: | :--------------------------------------------------------------: |
    |     `VDD_APC0`    | Power domain for Cluster0 CPU cores and L3 cache digital circuit |
    |     `VDD_APC1`    | Power domain for Cluster1 CPU cores and L3 cache digital circuit |
    |     `Chip_MX`     |        Power domain for the L1, L2, and L3 cache memories        |

    To know more about CPU core arrangement, see [IQ-9075 Data Sheet](https://docs.qualcomm.com/bundle/publicresource/topics/80-73417-1/device-description.html).
  </Tab>

  <Tab title="IQ-8275">
    > > APSS is a set of CPUs organized into clusters. All CPU cores in a cluster operate at a similar frequency. Each CPU core in a cluster has a dedicated L1 and L2 cache.
    > >
    > > The CPU subsystem consists of three clusters and L3 cache as follows:
    >
    > * Kryo Prime cluster with performance CPU cores
    > * Kryo Gold cluster, which has CPU cores with balanced power and performance
    > * Kryo Silver cluster, which has low power CPU cores for lightweight applications
    > * Silver cluster has a dedicated L3 cache
    > * Gold and Prime clusters share a dedicated L3 cache

    >     <img src="https://mintcdn.com/qualcomm-prod/OKFyShYzKWv2bmj8/System/Power/media/k2c-perf/cpu_arch_qcs8275.png?fit=max&auto=format&n=OKFyShYzKWv2bmj8&q=85&s=a25f315a74164afc8bbd859ed9b6d32c" alt="IQ-8275 CPUSS Architecture" width="932" height="625" data-path="System/Power/media/k2c-perf/cpu_arch_qcs8275.png" />
    >
    > > **Figure : IQ-8275 APSS CPU subsystem architecture**
    >
    > > The CPU subsystem operates on two power domains, each supplied by a dedicated SMPS rail.
    > >
    > > The following are the supported power domains:
    > >
    > > |                   | **Table : Power domains and their descriptions**                                   |
    > > | ----------------- | ---------------------------------------------------------------------------------- |
    > > | **Power domains** | **Description**                                                                    |
    > > | `VDD_APC0`        | Power domain for the Gold and Prime cluster CPU cores and L3 cache digital circuit |
    > > | `VDD_APC1`        | Power domain for the Silver cluster CPU cores and L3 cache digital circuit         |
    > > | `Chip_MX`         | Power domain for the L1, L2, and L3 cache memories                                 |

    To know more about CPU core arrangement, see [IQ-8275 Data Sheet](https://docs.qualcomm.com/bundle/publicresource/topics/80-73475-1/device-description.html).
  </Tab>

  <Tab title="IQ-615">
    > APSS is a set of CPUs organized into clusters. All CPU cores in a cluster operate at a similar frequency. Each CPU core in a cluster has a dedicated L1 and L2 cache.

    The CPU subsystem consists of two clusters and L3 cache as follows:

    * Qualcomm<sup>®</sup> Kryo<sup>™</sup> Gold cluster, which has CPU cores with balanced power and performance
    * Kryo Silver cluster, which has low power CPU cores for lightweight applications
    * Common L3 cache

    >     <img src="https://mintcdn.com/qualcomm-prod/OKFyShYzKWv2bmj8/System/Power/media/k2c-perf/talos_architecture.png?fit=max&auto=format&n=OKFyShYzKWv2bmj8&q=85&s=bcb8e6c1bd2d8cdcdc656c1ad0c134c7" alt="IQ-615 CPUSS Architecture" width="768" height="517" data-path="System/Power/media/k2c-perf/talos_architecture.png" />
    >
    > **Figure : IQ-615 APSS CPU subsystem architecture**
    >
    > >
    >
    > The CPU subsystem operates on two power domains, each supplied by a dedicated SMPS rail.
    >
    > The following are the supported power domains:
    >
    > |                   | **Table : Power domains and their descriptions**                           |
    > | ----------------- | -------------------------------------------------------------------------- |
    > | **Power domains** | **Description**                                                            |
    > | `VDD_APC0`        | Power domain for the Silver cluster CPU cores and L3 cache digital circuit |
    > | `VDD_APC1`        | Power domain for the Gold cluster CPU cores                                |
    > | `Chip_MX`         | Power domain for the L1, L2, and L3 cache memories                         |

    To know more about CPU core arrangement, see [IQ-615 Data Sheet](https://docs.qualcomm.com/bundle/publicresource/topics/80-73480-1/device-description.html).
  </Tab>

  <Tab title="IQ-X7181">
    > APSS is a set of CPUs organized into clusters. All CPU cores in a cluster operate at a similar frequency. Each CPU core in a cluster has a dedicated L1 cache and each cluster has a dedicated L2 cache.

    The CPU subsystem is organized into three clusters, each with its own dedicated L2 cache:

    * NCC Efficiency Cluster 0, which has 4 Qualcomm Oryon<sup>™</sup> CPU efficiency cores for lightweight applications
    * NCC Performance Cluster 1, which has 4 Oryon Performance CPU cores for balanced power and performance workloads
    * NCC Performance Cluster 2, which has 4 Oryon Performance CPU cores for balanced power and performance workloads
    * Shared L2 cache per each cluster

    >     <img src="https://mintcdn.com/qualcomm-prod/OKFyShYzKWv2bmj8/System/Power/media/k2c-perf/hamoa_cpuss_block_diagram.png?fit=max&auto=format&n=OKFyShYzKWv2bmj8&q=85&s=859fcd9c468e9858ebb65312b76cfadb" alt="IQ-X7181 CPUSS Architecture" width="1536" height="717" data-path="System/Power/media/k2c-perf/hamoa_cpuss_block_diagram.png" />
    >
    > **Figure : IQ-X7181 APSS CPU subsystem architecture**
    >
    > >
    >
    > The CPU subsystem uses separate logic and memory power domains for each cluster. Each domain is powered by its own dedicated SMPS rail.
    >
    > Following are the supported power domains:
    >
    > |                   | **Table : Power domains and their descriptions**                       |
    > | ----------------- | ---------------------------------------------------------------------- |
    > | **Power domains** | **Description**                                                        |
    > | `VDD_CLUSTER0_CX` | Logic power domain for the NCC Efficiency cluster 0 CPU cores          |
    > | `VDD_CLUSTER0_MX` | Memory power domain for the NCC Efficiency cluster 0 L1 and L2 caches  |
    > | `VDD_CLUSTER1_CX` | Logic power domain for the NCC Performance cluster 1 CPU cores         |
    > | `VDD_CLUSTER1_MX` | Memory power domain for the NCC Performance cluster 1 L1 and L2 caches |
    > | `VDD_CLUSTER2_CX` | Logic power domain for the NCC Performance cluster 2 CPU cores         |
    > | `VDD_CLUSTER2_MX` | Memory power domain for the NCC Performance cluster 2 L1 and L2 caches |
  </Tab>

  <Tab title="IQ-X5121">
    > APSS is a set of CPUs organized into clusters. All CPU cores in a cluster operate at a similar frequency. Each CPU core in a cluster has a dedicated L1 cache and each cluster has a dedicated L2 cache.

    The CPU subsystem consists of two clusters and a dedicated L2 cache as follows:

    * NCC Performance Cluster 0, which has 4 Qualcomm Oryon Performance CPU cores for balanced power and performance workloads
    * NCC Performance Cluster 1, which has 4 Qualcomm Oryon Performance CPU cores for balanced power and performance workloads
    * Shared L2 cache per each cluster

    >     <img src="https://mintcdn.com/qualcomm-prod/OKFyShYzKWv2bmj8/System/Power/media/k2c-perf/purwa_cpuss_block_diagram.png?fit=max&auto=format&n=OKFyShYzKWv2bmj8&q=85&s=0153e875260046c3ce2b582d372d4635" alt="IQ-X5121 CPUSS Architecture" width="1196" height="662" data-path="System/Power/media/k2c-perf/purwa_cpuss_block_diagram.png" />
    >
    > **Figure : IQ-X5121 APSS CPU subsystem architecture**
    >
    > >
    >
    > The CPU subsystem operates on dedicated logic and memory power domains for each cluster. Each domain is powered by its own dedicated SMPS rail.
    >
    > Following are the supported power domains:
    >
    > |                   | **Table : Power domains and their descriptions**                       |
    > | ----------------- | ---------------------------------------------------------------------- |
    > | **Power domains** | **Description**                                                        |
    > | `VDD_CLUSTER0_CX` | Logic power domain for the NCC Performance cluster 0 CPU cores         |
    > | `VDD_CLUSTER0_MX` | Memory power domain for the NCC Performance cluster 0 L1 and L2 caches |
    > | `VDD_CLUSTER1_CX` | Logic power domain for the NCC Performance cluster 1 CPU cores         |
    > | `VDD_CLUSTER1_MX` | Memory power domain for the NCC Performance cluster 1 L1 and L2 caches |
  </Tab>

  <Tab title="CQ-2390">
    > APSS is a set of CPUs organized into clusters. All CPU cores in a cluster operate at a similar frequency.

    The CPU subsystem consists of a single cluster and a common L3 cache:

    * 1 Cortex-A78c CPU core with dedicated L1 and L2 caches for balanced power and performance workloads
    * Common L3 cache

    >     <img src="https://mintcdn.com/qualcomm-prod/OKFyShYzKWv2bmj8/System/Power/media/k2c-perf/shikra_cpuss_block_diagram.png?fit=max&auto=format&n=OKFyShYzKWv2bmj8&q=85&s=aba0fa5f9a84c6b7e2503a1c5928a315" alt="CQ-2390 CPUSS Architecture" width="1099" height="686" data-path="System/Power/media/k2c-perf/shikra_cpuss_block_diagram.png" />
    >
    > **Figure : CQ-2390 APSS CPU subsystem architecture**
    >
    > >
    >
    > The CPU subsystem operates on one power domain supplied by a dedicated SMPS rail.
    >
    > Following are the supported power domains:
    >
    > |                   | **Table : Power domains and their descriptions**                                       |
    > | ----------------- | -------------------------------------------------------------------------------------- |
    > | **Power domains** | **Description**                                                                        |
    > | `VDD_APC0`        | Power domain for the Cortex-A55 and Cortex-A78c CPU cores and L3 cache digital circuit |
    > | `Chip_MX`         | Power domain for the L1, L2, and L3 cache memories                                     |
  </Tab>
</Tabs>