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The following table lists the device interface features for the Dragonwing IQ-8275. Table : Dragonwing IQ-8275 device interfaces
2xQUP v3 serial engine
Serial engine instancesQUPV3_0QUPV3_1
Application processor QUP v3 serial engine88
2xUSB controller
Controller address0xa6000000xa400000
Maximum speedUSB 3.x SuperSpeedUSB 2.0 high speed
HS/SS PHY power rails
  • L17A: VDDA-PHY-SUPPLY
  • L15A: VDDA-PLL-SUPPLY
  • L17A: VDDA-PLL-SUPPLY
  • L18C: VDDA
  • L19A: VDDA33-SUPPLY
  • L17A: VDDA-PLL-SUPPLY
  • L17C: VDDA18-SUPPLY
  • L19A: VDDA33-SUPPLY
2xPCIe controller
Root complexRC1RC0
SpeedGen4 2L (16 GT/s)Gen4 4L (16 GT/s)
Configuration space0x40100000 (0x100000) 1 MB0x60100000 (0x100000) 1 MB
I/O space0x40200000 (0x100000) 1 MB0x60200000 (0x100000) 1 MB
Base address register space (BAR)0x40300000 (0x1fd00000) 509 MB0x60300000 (0x1fd00000) 509 MB
Power rails
  • vreg_l6a (VDD_A_PCIE_0_CORE)
  • vreg_l5a (VDD_A_PCIE_0_PLL_1P2)
  • vreg_l5a (VDD_A_PCIE_1_CORE)
  • vreg_l6a (VDD_A_PCIE_1_PLL_1P2)
InterruptsMSI and PCI legacy interruptsMSI and PCI legacy interrupts
Power managementASPM (L1/L1ss, L0s)ASPM (L1/L1ss, L0s)

QUP v3 mapping to protocols and GPIOs in Dragonwing IQ-8275

Dragonwing IQ-8275 has two QUP v3 serial engines. The following table lists the protocol and GPIO mapping. Table : Dragonwing IQ-8275 QUP v3 serial engine protocol mapping
QUP v3 serial engineProtocolsQUP lane to GPIO mapping
UARTHS UARTI2C-MSPI-ML0L1L2L3L4L5L6
QUP_0SE0Yes–YesYes17181920–––
SE1Yes–YesYes19201718–––
SE2YesYesYesYes33343536–––
SE3YesYesYesYes25262728–––
SE4Yes–YesYes29303132–––
SE5Yes–YesYes21222324–––
SE6Yes–YesYes80818283–––
SE7Yes–YesYes43444344–––
QUP_2SE0Yes–YesYes37383940–––
SE1Yes–YesYes39403738–––
SE2YesYesYesYes8485868788––
SE3YesYesYesYes41424142–––
SE4Yes–YesYes45464748–––
SE5Yes–YesYes49505152–––
SE6Yes–YesYes89909192–––
SE7Yes–YesYes91928990–––