CPUIdle states and governors
CPUIdle manages idle state selection when a CPU has no runnable tasks. On Qualcomm platforms, idle states are defined in the device tree and communicated to Linux through the PSCI (Power State Coordination Interface) firmware.Idle state hierarchy
Qualcomm ARM64 SoCs typically expose three PSCI-backed idle states per CPU: Table: Typical Qualcomm PSCI idle states| State | PSCI state ID | Target residency | Description |
|---|---|---|---|
| WFI (C1) | 0x00000000 | ~1 µs | CPU clock gated; cache retained. Fastest entry and exit. |
| Core power-down (C2) | 0x00000003 | ~100 µs | CPU powered down; L1/L2 flushed. State retained in DDR. |
| Cluster power-collapse (C3) | 0x00000F03 | ~1–3 ms | Entire cluster powered off; L3 may be flushed. |
Inspect idle states at runtime
CPUIdle governors
Table: CPUIdle governors| Governor | Behavior |
|---|---|
menu | Default for tickless systems. Uses historical idle duration patterns and the next timer event to predict residency. Suitable for general-purpose workloads. |
TEO | Timer Events Oriented. Selects idle state based on the distance to the next timer event, ignoring pattern history. Lower latency for workloads with irregular wakeup patterns. |
PM QoS latency constraints
Drivers and user space can prevent CPUs from entering deep idle states by registering a latency constraint. Per-CPU constraints via sysfs:Runtime PM for peripherals
Runtime PM allows individual peripheral devices to enter low-power states while the system is running. On Qualcomm SoCs, power domains are managed by the RPMh hardware resource manager through theqcom-rpmhpd driver.
Enable runtime PM in a driver
Monitor runtime PM state
<device>by the platform device name from/sys/bus/platform/devices/.
Qualcomm power domains
RPMh power domains are registered by theqcom-rpmhpd driver. Inspect registered domains:
Thermal throttling
The Linux thermal framework monitors temperature sensors and applies cooling actions when trip points are crossed. Qualcomm SoCs expose thermal zones through TSENS (temperature sensor) hardware, with cooling devices implemented as CPU frequency caps and CPU hotplug.Inspect thermal zones
Thermal governors
Table: Thermal governors| Governor | Behavior |
|---|---|
step_wise | Incremental cooling: increases cooling one step at a time per polling interval. |
power_allocator | Uses an Intelligent Power Allocator (IPA) power model. Recommended for Qualcomm SoCs when an Energy Model is available. |
bang_bang | Binary on/off cooling based on trip hysteresis. |
System suspend (S2RAM)
System suspend powers off most SoC subsystems while retaining DRAM in self-refresh. On Qualcomm platforms, the suspend path issues a PSCISYSTEM_SUSPEND call in EL3, and the RPMh hardware sequencer powers down voltage rails in dependency order.
Trigger and verify suspend
Identify suspend blockers
Wakeup sources that are active prevent the system from suspending. Identify them:Debug suspend failures
Enable per-device suspend and resume tracing:Regulator and clock management
Reducing unnecessary always-on regulators and unused clock consumers can significantly reduce static power draw.Regulator state
Inspect all regulators and their enable state:regulator-always-on from DT bindings of optional peripherals (for example, MIPI-CSI sensors not populated on all boards) to allow runtime power gating. Retain it only for critical rails:
Clock tree
The Qualcomm clock controllers (GCC, CAMCC, DISPCC, and others) are managed by theclk-qcom driver family. Inspect enabled clocks:
devm_clk_get_enabled() (available since kernel v5.20) in drivers to acquire, enable, and automatically release a clock when the device is unbound or runtime-suspended:
Power analysis tools
powertop
powertop identifies power consumers, reports idle state residency, and shows per-process wakeup event rates:
- C-state residency: deep idle states (C2/C3) should exceed 80% residency when the system is idle.
- Wakeups/s: any single source exceeding 50 wakeups per second warrants investigation.

