Power management and resource control - Qualcomm Dragonwing Documentation

Manage how the MCU transitions between active and low-power states while maintaining correct resource usage and system behavior. Understand how clocks, power rails, and memory dependencies are asserted and released, how wake and resume flows are handled, and how power states impact interface stability. This helps you optimize power efficiency without compromising reliability, ensuring predictable wake behavior, stable data transfers, and correct restoration of system context after low-power operation. 7.1 Power modes overview The following table describes multiple run and sleep states that span clock gating, power gating, partial or full collapse, and reduced-frequency operation. Match the depth of the state to the amount of idle time you expect and the wake latency you can tolerate Table 7-1 Power mode states

State	Description
D0	▪ Fully active ▪ Use it for bring-up ▪ Baseline validation ▪ Active tasks
D1	Use for lighter idle while keeping fast return capability and QTIMER wake support.
D2 collapse	▪ Deepest software-visible low-power behavior described in the source. ▪ It uses full clock gating with reduced frequency and power gating and has higher resume latency than D1.

7.2 Resource voting and resume flow ■ Assert clock, CX, and DDR dependencies before active work starts. ■ Keep the dependency asserted for the full duration of the transfer or computation. ■ Release the dependency when the active work is done. ■ On wake, restore clocks and power in the required order, reload saved context if needed, and resume from the designated restart or resume point. ■ Validate the active interface path immediately after resume so you know whether the restored state is still usable. 7.3 Low-power debug considerations ■ Capture logs and debug state on both entry and exit from the target power state. ■ Keep at least one small functional path active in your test plan so resume failure is easy to spot. ■ Measure wake latency across repeated runs. ■ Repeat the scenario under back-to-back transitions and with injected timeout or error conditions.