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A system-on-chip (SoC) sleep state is a low power mode that the entire SoC enters when the device is idle or not actively running any use cases.
  1. Review SoC Sleep state functionality.
    The SoC supports many sleep states based on resource availability:
    • DDR (Double data rate memory)
    • XO (Crystal oscillator) clock
    • (Chip_CX) (Digital power supply)
    • (Chip_MX) (Memory domains power supply)
Note The SoC sleep states are enabled on QCS6490/QCS5430 and Qualcomm® Dragonwing™ IQ-615.
  1. Understand sleep transition.
As the device transitions from active state to SoC sleep state, the power consumption decreases. For example, when the device is idle with no use cases running, it’s in the SoC sleep state (AOSD). This is the deepest sleep state and consumes the least power. In this state, the resources, such as, XO clock, memory, and power supply of digital and memory domains also enter their respective sleep states.
  1. Learn the SoC sleep states and their resource states:
Note The SoC sleep states listed in the table are for reference only. You can’t enable or disable SoC sleep states.
Table : SoC sleep states
Note If the debugfs node is empty, mount debug file system to access device debugfs nodes

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Verify system-on-chip sleep state

Transitioning to the sleep state significantly reduces power consumption. To ensure power efficiency, the device should enter sleep state, whenever it’s idle. To verify that the device has successfully entered sleep state, it’s essential to retrieve the SoC sleep statistics.
The following is a sample output: Count: 3 Last Entered At: 1087943710378 Last Exited At: 1088442890377 Accumulated Duration: 6668562002 The following table explains the output fields: Table : SoC sleep states output fields Note The 19.2 MHz XO clock determines the system tick frequency.

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