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The following figure shows the workflow to bring up Ethernet on the reference kits.
Ethernet bringup workflow
  • Flash the corresponding CDT on the device to ensure that the correct configuration is used for Ethernet bringup.
  • The QPS615 MAC driver and kernel configuration are enabled by default in the source code.
  • To bring up hardware configurations other than the configuration provided by Qualcomm, see Bring up alternate hardware enablement.
To bring up Ethernet functionality on RB3 Gen 2 Development Kit, do the following:
  1. The RB3 Gen 2 Development Kit comes with a preconfigured MAC address. Skip this step if you choose to use the same MAC address.
    Alternatively, to change the preconfigured MAC address on the device, perform the following steps:
    1. Bring down the interface. 
      ip link set <Interface_name> down
      For example: 
      ip link set enP1p5s0f0 down
    2. Assign the MAC address. 
      ip link set dev <Interface_name> address <MAC>
      For example: 
      ip link set dev enP15s0f0 address XX:XX:XX:YY:YY:YY
    3. Bring up the interface. 
      ip addr add <ip>/<prefix> dev <Interface_name>
ip link set dev <Interface_name> up
      For example: 
      ip addr add 169.254.227.235/16 dev enP1p5s0f0
ip link set dev enP1p5s0f0 up
      Sample output: 
      ip -s addr show dev enP1p5s0f1
enP1p5s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP group default qlen 1000
    link/ether 62:99:60:23:4d:52 brd ff:ff:ff:ff:ff:ff
    RX:  bytes packets errors dropped  missed   mcast
        105971     313      0       2       0       0
    TX:  bytes packets errors dropped carrier collsns
        145434     762      0       2       0       0
      This MAC address is valid only for the current boot cycle. On rebooting the device, the MAC address is updated with the address from persistent storage as described in Verify preconfigured MAC address.
  2. When the device is connected to a public network, the DHCP server connected to the network assigns an IP address automatically. If a dynamic IP address is not assigned to the device but Ethernet connectivity is required, configure a static IP address manually within the same subnet of the client. 
    ip addr add <ip>/<prefix> dev <Interface_name>
    For example: 
    ip addr add 169.254.227.235/16 dev enP1p5s0f0
    Sample output: 
    ip -s addr show dev enP1p5s0f1
enP1p5s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP group default qlen 1000
    link/ether 62:99:60:23:4d:52 brd ff:ff:ff:ff:ff:ff
    RX:  bytes packets errors dropped  missed   mcast
        105971     313      0       2       0       0
    TX:  bytes packets errors dropped carrier collsns
        145434     762      0       2       0       0
    This IP address is valid only for the current boot cycle. On rebooting the device, the IP address isn’t retained.
  3. Configure the MTU size for the data packets over the Ethernet interface. 
    ip link set dev <Interface_name> down

ip link set dev <Interface_name> mtu <mtu_size>

ip link set dev <Interface_name> up
    For example: 
    ip link set dev enP1p5s0f0 down

ip link set dev enP1p5s0f0 mtu 1500

ip link set dev enP1p5s0f0 up
    Sample output: 
    ip -s addr show dev enP1p5s0f1
enP1p5s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP group default qlen 1000
    link/ether 62:99:60:23:4d:52 brd ff:ff:ff:ff:ff:ff
    RX:  bytes packets errors dropped  missed   mcast
        105971     313      0       2       0       0
    TX:  bytes packets errors dropped carrier collsns
        145434     762      0       2       0       0

​
Bring up alternate hardware enablement

You can attach MAC/PHY components other than the hardware configuration provided by Qualcomm and bring them up. To replace QPS615 with other PCIe based MAC/PHY, see PCIe software support for QPS615 switch.
You must obtain the MAC/PHY driver and firmware from the respective vendor. Qualcomm isn’t responsible for these configuration changes.

​
Retain QPS615 PCIe and replace QEP8121/AQR113C

To retain QPS615 PCIe and replace QEP8121/AQR113C with other PHY components, do the following:
  1. Based on the attached PHY recommendations, update all the parameters in the arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-staging.dtso file.
  2. Compile the software. Sample code for QEP PHY: 
    qep_vreg: qep_vreg {
           compatible = "regulator-fixed";
           regulator-name = "qep_vreg";
           gpio = <&pm7325_gpios 8 0>;
           regulator-min-microvolt = <1800000>;
           regulator-max-microvolt = <1800000>;
           enable-active-high;
        };
pci@0,1 {
        interrupts-extended = <&tlmm 101 IRQ_TYPE_EDGE_FALLING>;
        interrupt-names = "wol_irq";
        phy-supply = <&qep_vreg>;
        pinctrl-names = "default";
        pinctrl-0 = <&napa_intn_wol_sig>;
        phy-reset-gpios = <&qps615 1 GPIO_ACTIVE_LOW>;
        reset-deassert-us = <20000>;
        };
    After flashing the modified software, the QPS615 driver scans the physical devices connected to it and matches the device tree information.
    A PHY may fail to load due to mismatch between the configuration in the .dtso file and actual recommendations for the PHY. In such cases, you must update the configuration in the .dtso file accordingly.

​
AQR PHY enablement

Though AQR PHY for 10 GbE is optional, it’s validated on reference RB3 Gen 2 Development Kit. When bringing up Ethernet with AQR PHY for the first time, flash the PHY firmware to the hardware once. The AQR PHY is then detected and the PHY driver is enabled by default.Qualcomm verified the following AQR PHY firmware on RB3 Gen 2 Development Kit:
  • Marvell firmware: AQR-G4_v5.6.1-QR_Marvell_NoSwap_XFI_ID44874_VER1836.cld
  • Marvell proprietary flashburn tool is recommended for flashing Marvell AQR113 PHY.
  • Contact Marvell Technology, Inc. to obtain the AQR PHY firmware.

​
Detect the PHY

To detect the PHY, do the following:
  1. Update the AQR PHY parameters in the arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-staging.dtso file.
  2. Compile the software. Sample code for AQR PHY: 
    aqr_vreg: aqr_vreg {
        compatible = "regulator-fixed";
        regulator-name = "aqr_vreg";
        gpio = <&pm7250b_gpios 4 0>;
        regulator-min-microvolt = <1800000>;
        regulator-max-microvolt = <1800000>;
        enable-active-high;
        };

pci@0,0 {
        interrupts-extended = <&tlmm 141 IRQ_TYPE_EDGE_FALLING>;
        interrupt-names = "wol_irq";
        phy-supply = <&aqr_vreg>;
        pinctrl-names = "default";
        pinctrl-0 = <&aqr_intn_wol_sig>;
        phy-reset-gpios = <&qps615 0 GPIO_ACTIVE_LOW>;
        reset-deassert-us = <221000>;

        gpio-controller;
        #gpio-cells = <2>;
        };
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