QSPI

QSPI DT node:
 
qspi: spi@88df000 {
        compatible = "qcom,qcs615-qspi",
                      "qcom,qspi-v1";
        reg = <0x0 0x088df000 0x0 0x1000>;

        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH 0>;

        clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
                <&gcc GCC_QSPI_CORE_CLK>;
        clock-names = "iface",
                      "core";

        interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
                        &config_noc SLAVE_QSPI QCOM_ICC_TAG_ACTIVE_ONLY>,
                        <&aggre1_noc MASTER_QSPI QCOM_ICC_TAG_ALWAYS
                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
        interconnect-names = "qspi-config",
                              "qspi-memory";

        power-domains = <&rpmhpd RPMHPD_CX>;
        operating-points-v2 = <&qspi_opp_table>;

        iommus = <&apps_smmu 0x160 0x0>;

        pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0123>;
        pinctrl-names = "default";

        #address-cells = <1>;
        #size-cells = <0>;

        status = "disabled";
};

QSPI Pinctrl:
    qspi_cs0: qspi-cs0-state {
        pins = "gpio44";
        function = "qspi";
        bias-disable;
        drive-strength = <6>;
    };

    qspi_data0123: qspi-data0123-state {
        pins = "gpio45", "gpio46", "gpio47", "gpio49";
        function = "qspi";
        bias-pull-down;
        drive-strength = <6>;
    };

    qspi_clk: qspi-clk-state {
        pins = "gpio48";
        function = "qspi";
        bias-pull-down;
        drive-strength = <6>;
    };

&qspi {
    status = "okay";
    flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0>;
        spi-max-frequency = <25000000>;
        spi-tx-bus-width = <4>;
        spi-rx-bus-width = <4>;
    };
};