RTSS overview

The RTSS delivers high real-time performance through an independent, highly integrated architecture that enhances computing, networking, and safety support. RTSS embodies the SoC-within-a-SoC concept. For IoT products, the RTSS supports bootup, reset use cases, dump collection, Low-power mode, real-time application development, and more. The RTSS operates as a separate subsystem and supports FreeRTOS, a free real-time operating system. In the current release, FreeRTOS is enabled on the IQ-9075 and IQ-8275 processors as a binary-only release with functionality limited to booting up the device, and initializing clocks and peripherals in IoT applications.

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RTSS boot flow

The RTSS boots up in parallel with the APSS boot flow. The following figure shows the sequence of tasks at different levels in the RTSS bootup process: The cold boot sequence in RTSS involves the following steps:

1. Reset state exit: The boot core exits the reset state and begins executing the RTSS PBL. The APSS PBL simultaneously exits the reset state and begins execution. For more details, see APSS cold boot flow.
2. PBL execution:
   • Initializes the phase-locked loops (PLLs) and clocks.
   • Loads and authenticates the RTSS image (boot code in the EL2 layer and FreeRTOS in the EL1 layer).
   • Jumps to the RTSS EL2.
3. EL2 image initialization:
   • Initializes core drivers such as clock, GPIO, temperature monitoring, voltage monitoring, UART, and I²C.
   • Initializes crash dump collection.
   • Hands over control to RTSS EL1.
4. EL1 image initialization:
   • Completes FreeRTOS initialization to schedule and start tasks.
   • Initializes dedicated peripherals such as QUP (I²C, SPI, and UART).
   • Shares DDR memory between the APSS and RTSS. Ensure that the mailbox software drivers on both APSS and RTSS use the dedicated DDR shared memory space for communication between APSS and RTSS.

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Next steps

• Get started with RTSS