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The Improved Inter-Integrated Circuit (I3C) interface provides a fast, low-cost, low-power, 2-wire digital interface for connected I3C devices.
I3C is supported for aDSP sensor communication only. It is not supported for Linux use cases.

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Overview

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Bus Characteristics

  • 2-wire serial interface (SDA + SCL) supporting up to 12.5 MHz
  • Backward compatible with legacy I2C devices on the same bus
  • Address phase: 400 kHz
  • Data phase: 12.5 MHz

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Advanced Features

  • In-band interrupt (IBI) support
  • Hot-join (dynamic device addition)
  • Synchronous timing and asynchronous timestamping
  • 8-bit data parity during write operations
  • Dynamic addressing of targets
  • Single Data Rate (SDR) mode
  • CCC (Common Command Codes) per MIPI I3C specification

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Data Phase Modes

ModeUsage
Push-pullI3C-capable devices
Open-drainMixed bus with I2C devices

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Packet Frame Structure

ComponentDescription
S / SrStart or Repeat Start condition
I3C Dynamic Address7-bit dynamic address assigned during enumeration
R/WDirection bit (1=Read, 0=Write)
ACKAcknowledge (SDA low)
Data8-bit data payload
TTransition bit (alternative to ACK/NACK)
PStop condition

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Bus Initialization

1

Controller Initialization

The I3C controller driver initializes the controller, including firmware loading and configuration settings.
2

Configuration and Device Database Reading

The driver reads the I3C configuration and device database:
  • List of I2C static address devices
  • List of I3C static address devices
  • Expected I3C dynamic devices (vendor ID, device ID, predefined dynamic address, associated drivers)
  • Optional hot-join allowed devices
3

Device Enumeration

The driver enumerates devices on the bus and assigns local addresses.
4

Bus Configuration

The driver writes bus configuration to the controller:
  • Operation frequency
  • Pure/legacy I2C mode
  • SDR/HDR enable/disable
  • IBI-capable devices and expected data bytes
5

Client Software Configuration

Client software receives the device list and configuration for I2C/I3C devices and hot-join devices.

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Software Configuration

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Firmware Loading

I3C firmware for the QUP v3 serial engine loads with SSC QUP during aDSP bootup. Configuration files: 
/ADSP.HT.5.5.c8/adsp_proc/core/settings/buses/qup_fw/config/<chipset>/fw_devcfg.c
/ADSP.HT.5.5.c8/adsp_proc/core/settings/buses/qup_fw/config/<chipset>/fw_devcfg.xml
Serial engine configuration example: 
se_cfg se0_cfg = { 0x80000, SE_PROTOCOL_I3C, GSI, TRUE, TRUE };
se_cfg se1_cfg = { 0x84000, SE_PROTOCOL_I3C, GSI, TRUE, TRUE };

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GPIO Configuration

{
  .instance_id = 1,
  .qup = QUP_SSC,
  .se_index = 0,
  .protocol_io_cfg = {
    TLMM_MAP(TLMM_GPIO_KEEPER,  TLMM_GPIO_2MA, TLMM_GPIO_KEEPER),   // SLEEP
    TLMM_MAP(TLMM_GPIO_NO_PULL, TLMM_GPIO_6MA, TLMM_GPIO_KEEPER),   // SPI
    TLMM_MAP(TLMM_GPIO_NO_PULL, TLMM_GPIO_2MA, TLMM_GPIO_NO_PULL),  // UART
    TLMM_MAP(TLMM_GPIO_PULL_UP, TLMM_GPIO_2MA, TLMM_GPIO_NO_PULL),  // I2C
    TLMM_MAP(TLMM_GPIO_PULL_UP, TLMM_GPIO_2MA, TLMM_GPIO_KEEPER)    // I3C
  },
  .se_exclusive = TRUE,
}

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Troubleshooting

  • Verify SDA/SCL connections and pull-up resistors (1–4.7 kΩ)
  • Confirm vendor ID and device ID match expected values
Verify SCL frequency is 400 kHz during address phase. Adjust clock divider settings in firmware configuration.
  • Verify hot-join is enabled in configuration
  • Add device to the hot-join allowed list (vendor ID + device ID)
  • Measure rise/fall times on SDA and SCL
  • Adjust pull-up resistor values
  • Reduce bus length or capacitance

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Common Error Codes

ErrorDescriptionSolution
ENXIODevice not foundVerify connection and enumeration
ETIMEDOUTTransfer timeoutCheck clock signals and device power
EIOI/O errorCheck signal quality and pull-ups
EPROTOProtocol errorVerify timing parameters

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Resources

  • MIPI I3C Specification
  • Qualcomm Linux Interfaces Guide
  • QUP v3 Serial Engine Documentation