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The Serial Peripheral Interface (SPI) is a synchronous, full-duplex, 4-wire serial bus.

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Signals

SignalDescription
MOSIController data output, target data input
MISOController data input, target data output
SCLKClock generated by the controller
CSChip-select (active low); up to 4 chip-select lines per bus

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Transfer Modes by Subsystem

SubsystemTransfer ModesMax SpeedNotes
LinuxFIFO, CPU DMA, GSI50 MHz4–32 bits per word; up to 4 CS
BootFIFO only50 MHzPolling mode; GSI not supported
aDSPFull/half duplex, synchronous50 MHzRaw bit-level; no framing or error checking

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Interface Components

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Device Tree Sources

PlatformFile
Dragonwing IQ-8275arch/arm64/boot/dts/qcom/sa8295p.dtsi

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APIs

SubsystemHeader
Linuxinclude/uapi/linux/spi/spidev.h, include/linux/spi/spi.h
Bootboot_images/boot/QcomPkg/Include/SpiApi.h
aDSPadsp_proc/core/api/buses/spi_api.h

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Software Configuration

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Linux Device Tree Example

spi@a98000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a98000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
    interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SA8295P_CX>;
    dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
           <&gpi_dma1 1 6 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
};

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QUPAC Access Control

{ QUPV3_0_SE3, QUPV3_PROTOCOL_SPI, QUPV3_MODE_FIFO, AC_HLOS, TRUE,  TRUE, FALSE },
{ QUPV3_1_SE3, QUPV3_PROTOCOL_SPI, QUPV3_MODE_FIFO, AC_HLOS, FALSE, TRUE, TRUE  },
{ QUPV3_1_SE4, QUPV3_PROTOCOL_SPI, QUPV3_MODE_GSI,  AC_TZ,   FALSE, TRUE, TRUE  },
{ QUPV3_1_SE6, QUPV3_PROTOCOL_SPI, QUPV3_MODE_GSI,  AC_HLOS, FALSE, TRUE, FALSE },

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Configuration Steps

1

Enable kernel configurations

Edit kernel_platform/kernel/arch/arm64/configs/qcom_defconfig:
CONFIG_QCOM_GENI_SE=y
CONFIG_SPI_QCOM_GENI=m
CONFIG_SPI_SPIDEV=m
CONFIG_QCOM_GPI_DMA=m
2

Enable SPI node in device tree

&spi1 {
    status = "okay";
};
3

Compile and flash

Compile the kernel and device tree changes, then load images to the device.

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Verification

1

Transfer spidev_test to device

scp spidev_test ubuntu@<device_ip>:/bin
chmod 777 /bin/spidev_test
2

Run test

./spidev_test -D /dev/spidev1.0
Expected output:
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 KHz)

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Debugging

sudo su
mount -t debugfs none /sys/kernel/debug
echo -n "file spi-geni-qcom.c +p" > /sys/kernel/debug/dynamic_debug/control
echo -n "file spidev.c +p" > /sys/kernel/debug/dynamic_debug/control
echo -n "file gpi.c +p" > /sys/kernel/debug/dynamic_debug/control

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Troubleshooting

cat /boot/config-$(uname -r) | grep -i spi
dmesg | grep -i spi
  • Verify SPI node status is "okay" in device tree
  • Verify QUPAC_Access.c sets QUPV3_PROTOCOL_SPI, AC_HLOS, bLoad=TRUE
./spidev_test -D /dev/spidev1.0 -s 1000000
  • Check GPIO drive strength and pull configuration
  • Verify clock phase and polarity match the target device
  • Verify CONFIG_QCOM_GPI_DMA=m
  • Check dmas and dma-names in device tree
  • Verify QUPAC_Access.c sets QUPV3_MODE_GSI

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