SPI - Qualcomm Dragonwing Documentation

SPI features

Subsystem	Transfer mode	Description
RTSS	FIFO	Supports transfer rates up to 50 MHz. The host sets the SPI clock frequency nearest to the requested frequency. Supports maximum of 4 chip selects (CS) per bus.

SPI interface components

The devicetree source is at sail_proc/BSP/scripts/lemansau-sailhyp.dts.
SPI APIs The SPI APIs for the RTSS are listed at:

sail_proc/BSP/spi/public/Spi_Cfg.h
sail_proc/BSP/spi/public/Spi.h
sail_proc/BSP/spi/public/Spi_PBcfg.h
sail_proc/BSP/spi/public/Spi_Task.h

SPI software devicetree configuration

To enable SPI, configure SPI using the devicetree node. The following is an example of devicetree node:

s4_spi: qupv3_se4_spi {
                  reg-base = <0xF1910000>;
                  clock-name = "sailss_cc_qupv3_wrap0_s4_clk";
                  clock-frequency = <100000000>;
                  interrupt = <406>;
                  pinctrl = &se4_spi_pinctrl;
                  slave = <0>;
                  no-of-channels = <2>;
                  loopback  = <0>;
                  access-mode= <1>;
                  status = <1>;
};

Verify SPI interface

For information about verifying the SPI interface, see the spi section in RTSS test commands.

​SPI features

​SPI interface components

​SPI software devicetree configuration

​Verify SPI interface

SPI features

SPI interface components

SPI software devicetree configuration

Verify SPI interface