RTSS interfaces overview - Qualcomm Dragonwing Documentation

QUP v3 is a flexible and programmable module for supporting a wide range of serial interfaces such as I2C, SPI, and UART. The table lists the default QUP configurations on the device:

RTSS QUP	Protocol	Qualcomm Dragonwing^TM IQ-9075 pins	Qualcomm Dragonwing^TM IQ-8275 pins
RTSS_QUP0_SE_0	i2c0	0, 1	0, 1
RTSS_QUP0_SE_2	uart1 Debug	6, 7	8, 9
RTSS_QUP0_SE_3	i2c1	8, 9	10, 11
RTSS_QUP0_SE_4	spi0/can	10, 11, 12, 13, 14	14, 15, 16, 17, 18

RTSS has five RTSS_QUP serial engines (SEs). Each QUP SE has up to seven lanes (I/O) numbered from 0 to 6. You can select only one protocol for one QUP SE at a time. For example, RTSS doesn’t support simultaneous UART and I²C functionality. The supported assignments are listed in the table for each QUP:

IQ-9075
IQ-8275

The following tables provide information about the RTSS_QUP assignments and QUP lane to RTSS I/O mapping:

RTSS QUP core instance (tile)	Serial engine	UART (64 B FIFO)	HS UART (128 B FIFO)	I²C controller	SPI controller	SPI target	QUP lane to RTSS I/O mapping
L0	L1	L2	L3	L4	L5	L6
RTSS_QUP0	RTSS_QUP0_SE_0	Yes	–	Yes	Yes	Yes	0	1	6	7	–	–	–
RTSS_QUP0_SE_2	Yes	Yes	Yes	Yes	–	8	9	6	7	–	–	–
RTSS_QUP0_SE_3	Yes	Yes	Yes	Yes	–	8	9	4	5	–	–	–
RTSS_QUP0_SE_4	Yes	–	Yes	Yes	–	10	11	12	13	14	–	–

The following tables provide information about the RTSS_QUP assignments and QUP lane to RTSS I/O mapping:

RTSS QUP core instance (tile)	Serial engine	UART (64 B FIFO)	HS UART (128 B FIFO)	I²C controller	SPI controller	SPI target	QUP lane to RTSS I/O mapping
L0	L1	L2	L3	L4	L5
QUP0	QUP0_SE_0	Yes	–	Yes	Yes	Yes	0	1	2	3	–	–
QUP0_SE_2	Yes	Yes	Yes	Yes	–	12	13	8	9	–	–
QUP0_SE_3	Yes	Yes	Yes	Yes	–	10	11	12	13	–	–
QUP0_SE_4	Yes	–	Yes	Yes	–	14	15	16	17	18	–

QUP v3 serial engine customization

All serial engines in QUP v3 can be configured to specific interfaces such as I²C, UART, or SPI. The following use case defines the default protocol assigned to each enabled serial engine. You can modify the configuration based on board design.

aliases {
  i2c0   = &se0_i2c;
  uart0  = &se1_uart;
  uart1  = &se2_uart;
  i2c1   = &se3_i2c;
  spi0   = &se4_spi;
  ospi0  = &spinor_monaco;
  ospi1  = &spinor_lemans;
};

If SE0 is enabled by default as an I²C interface, you can reconfigure it as SPI by updating the aliases as shown in the following example:

aliases {
    uart0  = &se1_uart;     //remove i2c0
    uart1  = &se2_uart;
    i2c1   = &se3_i2c;
    spi0   = &se4_spi;
    spi1   = &se0_spi;     //add spi1
    ospi0  = &spinor_monaco;
    ospi1  = &spinor_lemans;
  };

​QUP v3 serial engine customization

QUP v3 serial engine customization