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The following table lists the device interface features in Dragonwing IQ-615. Table : Dragonwing IQ-615 device interfaces
2xQUP v3 serial engine
Serial engine instancesQUPV3_0QUPV3_1
Application processor QUP v3 serial engine43
2xUSB controller
Controller address0xa6000000xa800000
Max speedUSB 3.x SuperSpeedUSB 2.0 high speed
HS/SS PHY power rails
  • L4A: VDDD_QUSB_0_HS0_0P9
  • L11A: VDDA_QUSB_0_HS0_1P8
  • L17A: VDDA_QUSB_0_HS0_3P1
  • L4A: VDDD_QUSB_1_HS0_0P9
  • L11A: VDDA_QUSB_1_HS0_1P8
  • L17A: VDDA_QUSB_1_HS0_3P1
1xPCIe controller
Root complexRC0 (0x1c08000)
SpeedGen2
Configuration space0x40100000 (0x100000) 1 MB
I/O space0x40200000 (0x100000) 1 MB
Base address register space (BAR)0x40300000 (0x1fd00000) 509 MB
Power rails
  • L12A (vreg-1p2-supply)
  • L5A (vreg-0p9-supply)
InterruptsMSI and PCI legacy interrupts
Power managementASPM (L1/L1ss, L0s)

QUP v3 mapping to protocols and GPIOs in Dragonwing IQ-615

Dragonwing IQ-615 has two QUP v3 serial engines. The following table list the protocol and GPIO mapping. Table : Dragonwing IQ-615 QUP v3 serial engine protocol mapping
QUP v3 serial engineProtocolsQUP lane to GPIO mapping
UARTHS UARTI2C-MSPI-ML0L1L2L3L4L5L6
QUP_0SE0YesYesYes20212223
SE1Yes1415
SE2YesYesYes6789
SE3YesYesYesYes10111213
QUP_1SE1Yes45
SE2YesYesYes0123
SE3Yes1819