Dragonwing IQ-615 interface overview

The following table lists the device interface features in Dragonwing IQ-615. Table : Dragonwing IQ-615 device interfaces

3xQUP v3 serial engine
Serial engine instances	QUPV3_0	QUPV3_1
Application processor QUP v3 serial engine	4	4
LPI QUP v3 serial engine	5	–
2xUSB controller
Controller address	0xa600000	0xa800000
Max speed	USB 3.x SuperSpeed	USB 2.0 high speed
HS/SS PHY power rails	L4A: VDDD_QUSB_0_HS0_0P9 L11A: VDDA_QUSB_0_HS0_1P8 L17A: VDDA_QUSB_0_HS0_3P1	L4A: VDDD_QUSB_1_HS0_0P9 L11A: VDDA_QUSB_1_HS0_1P8 L17A: VDDA_QUSB_1_HS0_3P1
1xPCIe controller
Root complex	RC0 (0x1c08000)	–
Speed	Gen2	–
Configuration space	0x40100000 (0x100000) 1 MB	–
I/O space	0x40200000 (0x100000) 1 MB	–
Base address register space (BAR)	0x40300000 (0x1fd00000) 509 MB	–
Power rails	L12A (vreg-1p2-supply) L5A (vreg-0p9-supply)	–
Interrupts	MSI and PCI legacy interrupts	–
Power management	ASPM (L1/L1ss, L0s)	–

QUP v3 mapping to protocols and GPIOs in Dragonwing IQ-615

Dragonwing IQ-615 has three QUP v3 serial engines: two application-processor QUPs and one LPI QUP. The following table lists the protocol and GPIO mappings. Table : Dragonwing IQ-615 QUP v3 serial engine protocol mapping

QUP v3 serial engine		Protocols				QUP lane to GPIO mapping
		UART	HS UART	I2C-M	SPI-M	L0	L1	L2	L3	L4	L5	L6
QUP_0	SE0	Yes	–	–	–	16	17	–	–	–	–	–
	SE1	–	–	Yes	–	4	5	–	–	–	–	–
	SE2	Yes	–	Yes	Yes	0	1	2	3	–	–	–
	SE3	–	–	Yes	–	18	19	–	–	–	–	–
QUP_1	SE0	Yes	–	Yes	Yes	20	21	22	23	–	–	–
	SE1	–	–	Yes	–	14	15	–	–	–	–	–
	SE2	Yes	–	Yes	Yes	6	7	8	9	–	–	–
	SE3	Yes	Yes	Yes	Yes	10	11	12	13	–	–	–
LPI_QUP	SE0	–	–	Yes	–	0	1	–	–	–	–	–
	SE1	–	–	Yes	Yes	2	3	4	5	6	7	–
	SE2	–	–	Yes	Yes	8	9	10	11	–	–	–
	SE3	Yes	–	Yes	–	12	13	–	–	–	–	–
	SE4	Yes	–	Yes	–	14	15	–	–	–	–	–