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The following table lists the device interface features for QCS6490 and QCS5430. Table : QCS6490 and QCS5430 device interfaces
2xQUP v3 serial engine
Serial engine instancesQUPV3_0QUPV3_1
Application processor QUP v3 serial engine88
LPI QUP v3 serial engine5
2xUSB controller
Controller address0xa6000000x8c00000
Max SpeedUSB 3.x SuperSpeedUSB 2.0 high speed
HS/SS PHY power rails
  • L1C: VDD_A_USB_HS_1P8
  • L2B: VDD_A_USB_HS_3P1
  • L10C: VDD_A_USB_HS_CORE
  • L6B: VDD_A_USB_SS_DP_1P2
  • L1B: VDD_A_USB_SS_DP_CORE
  • L1C: VDD_A_USB_1_HS_1P8
  • L2B: VDD_A_USB_1_HS_3P1
  • L10C: VDD_A_USB_1_HS_CORE
2xPCIe controller
Root complexRC1RC0
SpeedGen3 2L (8 GT/s)Gen3 1L (8 GT/s)
Configuration space0x40100000 (0x100000) 1 MB0x60100000 (0x100000) 1 MB
I/O space0x40200000 (0x100000) 1 MB0x60200000 (0x100000) 1 MB
Base address register space (BAR)0x40300000 (0x3d00000)0x60300000 (0x1fd00000) 509 MB
Power rails
  • vreg_l0c (VDD_A_PCIE_0_CORE)
  • vreg_l6b (VDD_A_PCIE_0_PLL_1P2)
  • vreg_l0c (VDD_A_PCIE_1_CORE)
  • vreg_l6b (VDD_A_PCIE_1_PLL_1P2)
InterruptsMessage signaled interrupts (MSI) and peripheral component interconnect (PCI) legacy interruptsMSI and PCI legacy interrupts
Power managementActive-state power management (ASPM) L1/L1ss, L0sASPM (L1/L1ss, L0s)

QUP v3 mapping to protocols and GPIOs in QCS6490 and QCS5430

QCS6490 and QCS5430 contain 21 QUP v3 serial engines. Of these, 16 QUP v3 serial engines are allocated for the application processor and 5 QUP v3 serial engines are allocated for the sensor low-power island (SLPI) on the application digital signal processor (aDSP). Select only one protocol in a QUP v3 serial engine at a time. For example, simultaneous UART and I2C functions aren’t supported. Each QUP v3 serial engine has up to seven lanes (I/O), which are numbered from 0 to 6. Note The top-level QUP v3 serial engines are used as the application processor and boot image. The low-power island (LPI) QUP v3 serial engines are used for the sensor subsystem and Qualcomm® Trusted Execution Environment (TEE) use cases. The following table lists the default QUP v3 mapping to protocols and GPIOs. Table : QCS6490 and QCS5430 QUP v3 serial engine protocol mapping
QUP v3 serial engineProtocolsQUP lane to GPIO mapping
UARTI3CHS UARTSPI-MI2CL0L1L2L3L4L5L6
QUP_0SE0YesYesYesYes0123
SE1YesYesYesYes4567
SE2YesYesYes891011
SE3YesYesYes12131415
SE4YesYesYes16171819
SE5YesYesYes20212223
SE6YesYesYesYes24252627
SE7YesYesYesYes28293031236
QUP_1SE0YesYesYesYes32333435
SE1YesYesYesYes36373839
SE2YesYesYes40414243
SE3YesYesYes44454547
SE4YesYesYes48495051555438
SE5YesYesYes52535455
SE6YesYesYesYes56575859626350
SE7YesYesYesYes60616263
LPI_QUPSE0YesYes159160
SE1YesYes161162
SE2YesYesYes163164165166161
SE5YesYes171172171172
SE6YesYes159159