QCS6490 and QCS5430 interfaces overview

The following table lists the device interface features for QCS6490 and QCS5430. Table : QCS6490 and QCS5430 device interfaces

2xQUP v3 serial engine
Serial engine instances	QUPV3_0	QUPV3_1
Application processor QUP v3 serial engine	8	8
LPI QUP v3 serial engine	5	–
2xUSB controller
Controller address	0xa600000	0x8c00000
Max Speed	USB 3.x SuperSpeed	USB 2.0 high speed
HS/SS PHY power rails	L1C: VDD_A_USB_HS_1P8 L2B: VDD_A_USB_HS_3P1 L10C: VDD_A_USB_HS_CORE L6B: VDD_A_USB_SS_DP_1P2 L1B: VDD_A_USB_SS_DP_CORE	L1C: VDD_A_USB_1_HS_1P8 L2B: VDD_A_USB_1_HS_3P1 L10C: VDD_A_USB_1_HS_CORE
2xPCIe controller
Root complex	RC1	RC0
Speed	Gen3 2L (8 GT/s)	Gen3 1L (8 GT/s)
Configuration space	0x40100000 (0x100000) 1 MB	0x60100000 (0x100000) 1 MB
I/O space	0x40200000 (0x100000) 1 MB	0x60200000 (0x100000) 1 MB
Base address register space (BAR)	0x40300000 (0x3d00000)	0x60300000 (0x1fd00000) 509 MB
Power rails	vreg_l0c (VDD_A_PCIE_0_CORE) vreg_l6b (VDD_A_PCIE_0_PLL_1P2)	vreg_l0c (VDD_A_PCIE_1_CORE) vreg_l6b (VDD_A_PCIE_1_PLL_1P2)
Interrupts	Message signaled interrupts (MSI) and peripheral component interconnect (PCI) legacy interrupts	MSI and PCI legacy interrupts
Power management	Active-state power management (ASPM) L1/L1ss, L0s	ASPM (L1/L1ss, L0s)

QUP v3 mapping to protocols and GPIOs in QCS6490 and QCS5430

QCS6490 and QCS5430 contain 21 QUP v3 serial engines. Of these, 16 QUP v3 serial engines are allocated for the application processor and 5 QUP v3 serial engines are allocated for the sensor low-power island (SLPI) on the application digital signal processor (aDSP). Select only one protocol in a QUP v3 serial engine at a time. For example, simultaneous UART and I2C functions aren’t supported. Each QUP v3 serial engine has up to seven lanes (I/O), which are numbered from 0 to 6. Note The top-level QUP v3 serial engines are used as the application processor and boot image. The low-power island (LPI) QUP v3 serial engines are used for the sensor subsystem and Qualcomm® Trusted Execution Environment (TEE) use cases. The following table lists the default QUP v3 mapping to protocols and GPIOs. Table : QCS6490 and QCS5430 QUP v3 serial engine protocol mapping

QUP v3 serial engine		Protocols					QUP lane to GPIO mapping
		UART	I3C	HS UART	SPI-M	I2C	L0	L1	L2	L3	L4	L5	L6
QUP_0	SE0	Yes	Yes	–	Yes	Yes	0	1	2	3	–	–	–
	SE1	Yes	Yes	–	Yes	Yes	4	5	6	7	–	–	–
	SE2	Yes	–	–	Yes	Yes	8	9	10	11	–	–	–
	SE3	Yes	–	–	Yes	Yes	12	13	14	15	–	–	–
	SE4	Yes	–	–	Yes	Yes	16	17	18	19	–	–	–
	SE5	Yes	–	–	Yes	Yes	20	21	22	23	–	–	–
	SE6	Yes	–	Yes	Yes	Yes	24	25	26	27	–	–	–
	SE7	Yes	–	Yes	Yes	Yes	28	29	30	31	2	3	6
QUP_1	SE0	Yes	Yes	–	Yes	Yes	32	33	34	35	–	–	–
	SE1	Yes	Yes	–	Yes	Yes	36	37	38	39	–	–	–
	SE2	Yes	–	–	Yes	Yes	40	41	42	43	–	–	–
	SE3	Yes	–	–	Yes	Yes	44	45	45	47	–	–	–
	SE4	Yes	–	–	Yes	Yes	48	49	50	51	55	54	38
	SE5	Yes	–	–	Yes	Yes	52	53	54	55	–	–	–
	SE6	Yes	–	Yes	Yes	Yes	56	57	58	59	62	63	50
	SE7	Yes	–	Yes	Yes	Yes	60	61	62	63	–	–	–
LPI_QUP	SE0	–	Yes	–	–	Yes	159	160	–	–	–	–	–
	SE1	–	Yes	–	–	Yes	161	162	–	–	–	–	–
	SE2	–	Yes	–	Yes	Yes	163	164	165	166	161	–	–
	SE5	Yes	–	–	–	Yes	171	172	171	172	–	–	–
	SE6	Yes	–	Yes	–	–	159	159	–	–	–	–	–