Dragonwing IQ-X5121 interface overview

The following table lists the device interface features in Dragonwing IQ-X5121. Table : Dragonwing IQ-X5121 device interfaces

3xQUP v3 serial engine
Serial engine instances	QUPV3_0	QUPV3_1	QUPV3_2
Application processor QUP v3 serial engine	8	8	8
LPI QUP v3 serial engine	9	–	–
USB controller details
4xPCIe controller
Root complex	RC3	RC4	RC5	RC6a
Speed	Gen4 4L (16 GT/s)	Gen3 2L (8 GT/s)	Gen3 2L (8 GT/s)	Gen4 4L (16 GT/s)
Configuration space	0x78100000 (0x100000) 1 MB	0x7c100000 (0x100000) 1 MB	0x7e100000 (0x100000) 1 MB	0x70100000 (0x100000) 1 MB
I/O space	0x78200000 (0x100000) 1 MB	0x7c200000 (0x100000) 1 MB	0x7e200000 (0x100000) 1 MB	0x70200000 (0x100000) 1 MB
Base address register space (BAR)	0x78300000 (0x3d00000) 61 MB	0x7c300000 (0x1d00000) 29 MB	0x7e300000 (0x1d00000) 29 MB	0x70300000 (0x3d00000) 61 MB
Power rails	vreg_l3c_0p8 (PHY core) vreg_l3e_1p2 (PHY PLL)	vreg_l3i_0p8 (PHY core) vreg_l3e_1p2 (PHY PLL)	vreg_l3i_0p8 (PHY core) vreg_l3e_1p2 (PHY PLL)	vreg_l1d_0p8 (PHY core) vreg_l2j_1p2 (PHY PLL)
Interrupts	MSI and PCI legacy interrupts	MSI and PCI legacy interrupts	MSI and PCI legacy interrupts	MSI and PCI legacy interrupts
Power management	ASPM (L1/L1ss, L0s)	ASPM (L1/L1ss, L0s)	ASPM (L1/L1ss, L0s)	ASPM (L1/L1ss, L0s)

​

QUP v3 mapping to protocols and GPIOs in Dragonwing IQ-X5121

Dragonwing IQ-X5121 contains 33 QUP v3 serial engines. Of these, 24 QUP v3 serial engines are allocated for the application processor and 9 QUP v3 serial engines are allocated for the low-power island (LPI). Select only one protocol in a QUP v3 serial engine at a time. For example, simultaneous UART and I2C functions aren’t supported. The top-level QUP v3 serial engines are used by the application processor and boot image. The LPI QUP v3 serial engines are used by the sensor subsystem. The following table lists the default QUP v3 mapping to protocols and GPIOs. Table : Dragonwing IQ-X5121 QUP v3 serial engine protocol mapping

QUP v3 serial engine		Protocols				QUP lane to GPIO mapping
		UART	HS UART	I2C-M	SPI-M	L0	L1	L2	L3	L4	L5	L6
QUP_0	SE0	Yes	Yes	Yes	Yes	0	1	2	3	–	–	–
	SE1	Yes	Yes	Yes	Yes	4	5	6	7	–	–	–
	SE2	Yes	Yes	Yes	Yes	8	9	10	11	17	18	19
	SE3	Yes	Yes	Yes	Yes	12	13	14	15	23	22	21
	SE4	Yes	Yes	Yes	Yes	16	17	18	19	–	–	–
	SE5	Yes	Yes	Yes	Yes	20	21	22	23	–	–	–
	SE6	Yes	Yes	Yes	Yes	24	25	26	27	–	–	–
	SE7	Yes	Yes	Yes	Yes	14	15	12	13	–	–	–
QUP_1	SE0	Yes	Yes	Yes	Yes	32	33	34	35	–	–	–
	SE1	Yes	Yes	Yes	Yes	36	37	38	39	–	–	–
	SE2	Yes	Yes	Yes	Yes	40	41	42	43	49	50	51
	SE3	Yes	Yes	Yes	Yes	44	45	46	47	35	34	33
	SE4	Yes	Yes	Yes	Yes	48	49	50	51	–	–	–
	SE5	Yes	Yes	Yes	Yes	52	53	54	55	–	–	–
	SE6	Yes	Yes	Yes	Yes	56	57	58	59	–	–	–
	SE7	Yes	Yes	Yes	Yes	54	55	52	53	–	–	–
QUP_2	SE0	Yes	Yes	Yes	Yes	64	65	66	67	–	–	–
	SE1	Yes	Yes	Yes	Yes	68	69	70	71	–	–	–
	SE2	Yes	Yes	Yes	Yes	72	73	74	75	81	82	83
	SE3	Yes	Yes	Yes	Yes	76	77	78	79	67	66	65
	SE4	Yes	Yes	Yes	Yes	80	81	82	83	–	–	–
	SE5	Yes	Yes	Yes	Yes	84	85	86	87	–	–	–
	SE6	Yes	Yes	Yes	Yes	88	89	90	91	–	–	–
	SE7	Yes	Yes	Yes	Yes	86	87	84	85	–	–	–
LPI_QUP	SE0	–	–	Yes	–	215	216	–	–	–	–	–
	SE1	–	–	Yes	–	217	218	231	232	–	–	–
	SE2	–	–	Yes	Yes	219	220	221	222	223	–	–
	SE3	–	–	Yes	–	223	224	–	–	–	–	–
	SE4	–	–	Yes	Yes	225	226	227	228	221	222	–
	SE5	Yes	–	–	–	–	–	229	230	–	–	–
	SE6	Yes	–	Yes	–	231	232	231	232	–	–	–
	SE7	–	–	Yes	–	233	234	–	–	–	–	–
	SE8	–	–	Yes	–	235	236	–	–	–	–	–