| 1xQUP v3 serial engine | |
| Serial engine instances | QUPV3_0 |
| Application processor QUP v3 serial engine | 10 |
| USB controller details | |
| PCIe controller details | |
QUP v3 mapping to protocols and GPIOs in Dragonwing Shikra
Dragonwing Shikra contains 10 QUP v3 serial engines. All 10 QUP v3 serial engines are allocated for the application processor. The QUP v3 serial engines are numbered from SE0 to SE9. Select only one protocol in a QUP v3 serial engine at a time. For SE1 and SE9, the mirrored GPIO entries represent alternate GPIO pairs. Use only one GPIO pair for each lane at a time; do not use both mirror pairs simultaneously. The following table lists the default QUP v3 mapping to protocols and GPIOs. Table : Dragonwing Shikra QUP v3 serial engine protocol mapping| QUP v3 serial engine | Protocols | QUP lane to GPIO mapping | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| UART | HS UART | SPI-M | I2C-M | L0 | L1 | L2 | L3 | L4 | L5 | L6 | ||
| QUP_0 | SE0 | Yes | Yes | Yes | Yes | 2 | 3 | 0 | 1 | – | – | – |
| SE1 | Yes | – | Yes | Yes | 5 | 4 | 4, 28 | 5, 29 | – | – | – | |
| SE2 | Yes | – | Yes | Yes | 6 | 7 | 8 | 9 | 30 | 31 | – | |
| SE3 | Yes | – | – | Yes | 10 | 11 | 11 | 10 | – | – | – | |
| SE4 | Yes | – | – | Yes | 12 | 13 | 13 | 12 | – | – | – | |
| SE5 | Yes | – | Yes | Yes | 14 | 15 | 16 | 17 | – | – | – | |
| SE6 | Yes | Yes | Yes | Yes | 18 | 19 | 28 | 29 | 30 | 31 | – | |
| SE7 | Yes | – | – | Yes | 20 | 21 | 21 | 20 | – | – | – | |
| SE8 | Yes | Yes | Yes | Yes | 22 | 23 | 24 | 25 | – | – | – | |
| SE9 | Yes | Yes | Yes | Yes | 27, 48 | 26, 49 | 26, 50 | 27, 51 | – | – | – | |